URL https://opencores.org/ocsvn/tv80/tv80/trunk

Subversion Repositories tv80

[/] [tv80/] [trunk] - Rev 92

Rev	Log message	Author	Age	Path
69	Added UART instance in testbench, and added UART to compile list.	ghutchis	7050d 10h	/tv80/trunk
68	Updated nwtest to reflect changes in register interface to simple_gmii. In particular, interrupt bits for packet arrival and sending now need to be explicitly cleared afterwards.	ghutchis	7058d 10h	/tv80/trunk
67	Updated register generator based on testing with simple_gmii. Changed how interrupt output mux is created, fixed many bugs.	ghutchis	7058d 10h	/tv80/trunk
66	Modified top level testbench to reflect changes in simple_gmii block	ghutchis	7058d 11h	/tv80/trunk
65	Major restructuring of simple_gmii block. 1) Changed simple_gmii block to simple_gmii_core 2) Migrated RAM instances out of core into top level 3) Removed CPU interface logic and created CPU interface block using register generator 4) Changed status register to interrupt register and added interrupt logic	ghutchis	7058d 11h	/tv80/trunk
64	Created rgen script and expanded available register types	ghutchis	7059d 09h	/tv80/trunk
63	Added simple regression script. -r command runs all tests (serially), -c command checks results after all tests have completed.	ghutchis	7093d 14h	/tv80/trunk
62	Reset timeout counter whenever a message is printed	ghutchis	7093d 14h	/tv80/trunk
61	Added timeout disable for large buf sizes	ghutchis	7093d 14h	/tv80/trunk
60	Added ifdef TV80_REFRESH, to remove refresh logic by default. Also ran untabify to remove tabs from source code.	ghutchis	7093d 14h	/tv80/trunk