URL https://opencores.org/ocsvn/tv80/tv80/trunk

Subversion Repositories tv80

[/] [tv80/] [trunk] - Rev 97

Rev	Log message	Author	Age	Path
74	Changed default for T2Write to be 1, to match expected behavior for most users.	ghutchis	6920d 17h	/tv80/trunk
73	Added RC4 encrypt/decrypt test	ghutchis	6932d 12h	/tv80/trunk
72	Added copyright header	ghutchis	6932d 12h	/tv80/trunk
71	Ported UART from T80	ghutchis	6993d 16h	/tv80/trunk
70	Added test for T16450 UART	ghutchis	7044d 11h	/tv80/trunk
69	Added UART instance in testbench, and added UART to compile list.	ghutchis	7044d 11h	/tv80/trunk
68	Updated nwtest to reflect changes in register interface to simple_gmii. In particular, interrupt bits for packet arrival and sending now need to be explicitly cleared afterwards.	ghutchis	7052d 12h	/tv80/trunk
67	Updated register generator based on testing with simple_gmii. Changed how interrupt output mux is created, fixed many bugs.	ghutchis	7052d 12h	/tv80/trunk
66	Modified top level testbench to reflect changes in simple_gmii block	ghutchis	7052d 12h	/tv80/trunk
65	Major restructuring of simple_gmii block. 1) Changed simple_gmii block to simple_gmii_core 2) Migrated RAM instances out of core into top level 3) Removed CPU interface logic and created CPU interface block using register generator 4) Changed status register to interrupt register and added interrupt logic	ghutchis	7052d 12h	/tv80/trunk