URL https://opencores.org/ocsvn/tv80/tv80/trunk

Subversion Repositories tv80

[/] [tv80/] [trunk] - Rev 98

Rev	Log message	Author	Age	Path
75	Modified environment I/O so multicycle wr_n signals are only seen as a single write.	ghutchis	6918d 09h	/tv80/trunk
74	Changed default for T2Write to be 1, to match expected behavior for most users.	ghutchis	6918d 10h	/tv80/trunk
73	Added RC4 encrypt/decrypt test	ghutchis	6930d 04h	/tv80/trunk
72	Added copyright header	ghutchis	6930d 04h	/tv80/trunk
71	Ported UART from T80	ghutchis	6991d 08h	/tv80/trunk
70	Added test for T16450 UART	ghutchis	7042d 03h	/tv80/trunk
69	Added UART instance in testbench, and added UART to compile list.	ghutchis	7042d 03h	/tv80/trunk
68	Updated nwtest to reflect changes in register interface to simple_gmii. In particular, interrupt bits for packet arrival and sending now need to be explicitly cleared afterwards.	ghutchis	7050d 04h	/tv80/trunk
67	Updated register generator based on testing with simple_gmii. Changed how interrupt output mux is created, fixed many bugs.	ghutchis	7050d 04h	/tv80/trunk
66	Modified top level testbench to reflect changes in simple_gmii block	ghutchis	7050d 04h	/tv80/trunk