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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] - Rev 70

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Rev Log message Author Age Path
50 added WB_B4RAM with byte enable unneback 4768d 09h /versatile_library/trunk/rtl/verilog
49 added WB_B4RAM with byte enable unneback 4768d 09h /versatile_library/trunk/rtl/verilog
48 wb updated unneback 4775d 03h /versatile_library/trunk/rtl/verilog
46 updated parity unneback 4871d 08h /versatile_library/trunk/rtl/verilog
45 updated timing in io models unneback 4873d 02h /versatile_library/trunk/rtl/verilog
44 added target independet IO functionns unneback 4876d 02h /versatile_library/trunk/rtl/verilog
43 added logic for parity generation and check unneback 4880d 05h /versatile_library/trunk/rtl/verilog
42 updated mux_andor unneback 4884d 05h /versatile_library/trunk/rtl/verilog
41 typo in registers.v unneback 4884d 06h /versatile_library/trunk/rtl/verilog
40 new build environment with custom.v added as a result file unneback 4884d 07h /versatile_library/trunk/rtl/verilog

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