URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_altera.v] - Rev 47

Rev	Log message	Author	Age	Path
24	added vl_dff_ce_set	unneback	4921d 02h	/versatile_library/trunk/rtl/verilog/versatile_library_altera.v
23	fixed port map error in async fifo 1r1w	unneback	4921d 16h	/versatile_library/trunk/rtl/verilog/versatile_library_altera.v
22	added binary counters	unneback	4921d 21h	/versatile_library/trunk/rtl/verilog/versatile_library_altera.v
21	reg -> wire in and or mux in logic	unneback	4922d 18h	/versatile_library/trunk/rtl/verilog/versatile_library_altera.v
18	naming convention vl_	unneback	4924d 05h	/versatile_library/trunk/rtl/verilog/versatile_library_altera.v
17		unneback	4987d 18h	/versatile_library/trunk/rtl/verilog/versatile_library_altera.v
15	added delay line	unneback	4994d 02h	/versatile_library/trunk/rtl/verilog/versatile_library_altera.v
14	reg -> wire for various signals	unneback	4994d 07h	/versatile_library/trunk/rtl/verilog/versatile_library_altera.v
13	cosmetic update	unneback	4994d 08h	/versatile_library/trunk/rtl/verilog/versatile_library_altera.v
12	added wishbone comliant modules	unneback	4995d 04h	/versatile_library/trunk/rtl/verilog/versatile_library_altera.v