URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [tags/] [Rev1/] [rtl] - Rev 91

Rev	Log message	Author	Age	Path
66		unneback	5170d 15h	/versatile_mem_ctrl/tags/Rev1/rtl
65	added	unneback	5170d 15h	/versatile_mem_ctrl/tags/Rev1/rtl
64	Changed sdr 16 FSM to use defines instead of parameters which were somehow screwing up synplify, reinstated used of sdr_16_defines.v file	julius	5171d 15h	/versatile_mem_ctrl/tags/Rev1/rtl
63	Fixed a couple of sdr_16 bugs to do with tracking of opened banks	julius	5171d 22h	/versatile_mem_ctrl/tags/Rev1/rtl
62	Added note to sdr_16_defines.v asking if it's still used	julius	5172d 00h	/versatile_mem_ctrl/tags/Rev1/rtl
61	Fixed blocking/nonblocking assign issue in sdr_16 fsm	julius	5175d 23h	/versatile_mem_ctrl/tags/Rev1/rtl
60	Added synthesis directives ensuring registering of right signals in IOBs for sdr16 controller. Removed comment stripping from vppreproc command for sdr_16 creation.	julius	5175d 23h	/versatile_mem_ctrl/tags/Rev1/rtl
59	counter changed to shift register	unneback	5176d 00h	/versatile_mem_ctrl/tags/Rev1/rtl
58	sdr_16 fixes for timing - extra egress register stage, appropriate changes in sdr_16 fsm	julius	5177d 01h	/versatile_mem_ctrl/tags/Rev1/rtl
57	added support for early termination of burst access	unneback	5178d 04h	/versatile_mem_ctrl/tags/Rev1/rtl