URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [trunk] - Rev 113

Rev	Log message	Author	Age	Path
85	Added a versatile_mem_ctrl specific version of the flag generation module in the versatile fifo.	mikaeljf	5108d 20h	/versatile_mem_ctrl/trunk
84		mikaeljf	5112d 19h	/versatile_mem_ctrl/trunk
83		mikaeljf	5113d 14h	/versatile_mem_ctrl/trunk
82		mikaeljf	5113d 19h	/versatile_mem_ctrl/trunk
81		mikaeljf	5114d 15h	/versatile_mem_ctrl/trunk
80		mikaeljf	5114d 16h	/versatile_mem_ctrl/trunk
79	Added defines that fix bugs with slow wishbone clocks doing burst writes	julius	5152d 06h	/versatile_mem_ctrl/trunk
78	Burst writing working again, although its mostly hardcoded to burst 4. Also added a fix for when the RAM and bus clocks are about the same speed, to avoid buffer overrun	julius	5154d 13h	/versatile_mem_ctrl/trunk
77	SDR 16 registering of current_fifo_empty signal in top, appropriate control alterations in fsm_sdr_16	julius	5162d 11h	/versatile_mem_ctrl/trunk
76	Changed SDR16 synthesis useioff location, fsm_wb acking logic, default SDR build is for 16m part now	julius	5167d 12h	/versatile_mem_ctrl/trunk