URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [trunk] - Rev 34

Rev	Log message	Author	Age	Path
14	Added external feedback of DDR SDRAM clock.	mikaeljf	5427d 04h	/versatile_mem_ctrl/trunk
13	Modified DDR FSM for read and write, added counters for burst length, read/write latency, write recovery time etc. Added DCM with external feedback.	mikaeljf	5427d 07h	/versatile_mem_ctrl/trunk
12	Minor update of whishbone FSMs in TB	mikaeljf	5437d 08h	/versatile_mem_ctrl/trunk
11	Initial version with support for DDR	mikaeljf	5437d 20h	/versatile_mem_ctrl/trunk
10		unneback	5465d 04h	/versatile_mem_ctrl/trunk
9	testbench	unneback	5465d 04h	/versatile_mem_ctrl/trunk
8		unneback	5561d 00h	/versatile_mem_ctrl/trunk
7		unneback	5561d 00h	/versatile_mem_ctrl/trunk
6		unneback	5561d 00h	/versatile_mem_ctrl/trunk
5	pass initial testing	unneback	5561d 01h	/versatile_mem_ctrl/trunk