URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [trunk] - Rev 49

Rev	Log message	Author	Age	Path
29	Adapted the test bench to the new wishbone interface.	mikaeljf	5303d 21h	/versatile_mem_ctrl/trunk
28	Fixed typos and updated the rtl Makefile and Altera-Modelsim script. Modified the counter-excel file and added missing module 'dff_sr.v'.	mikaeljf	5303d 23h	/versatile_mem_ctrl/trunk
27		unneback	5307d 14h	/versatile_mem_ctrl/trunk
26	compiles OK, not simulated	unneback	5309d 13h	/versatile_mem_ctrl/trunk
25		unneback	5309d 16h	/versatile_mem_ctrl/trunk
24	Updated the memory controller according to recent update of Versatile_counter. Modified the rtl Makefile and added an excel file with counter definitions.	mikaeljf	5310d 03h	/versatile_mem_ctrl/trunk
23	Removed redundant code.	mikaeljf	5317d 20h	/versatile_mem_ctrl/trunk
22	Updated the Altera timing constraints file, also minor updates of defines file and Makefile.	mikaeljf	5319d 16h	/versatile_mem_ctrl/trunk
21	Updated the Altera timing constraints file (.sdc).	mikaeljf	5323d 19h	/versatile_mem_ctrl/trunk
20	Minor update of sdc-file.	mikaeljf	5325d 21h	/versatile_mem_ctrl/trunk