URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl] - Rev 46

Rev	Log message	Author	Age	Path
26	compiles OK, not simulated	unneback	5246d 09h	/versatile_mem_ctrl
25		unneback	5246d 11h	/versatile_mem_ctrl
24	Updated the memory controller according to recent update of Versatile_counter. Modified the rtl Makefile and added an excel file with counter definitions.	mikaeljf	5246d 23h	/versatile_mem_ctrl
23	Removed redundant code.	mikaeljf	5254d 15h	/versatile_mem_ctrl
22	Updated the Altera timing constraints file, also minor updates of defines file and Makefile.	mikaeljf	5256d 11h	/versatile_mem_ctrl
21	Updated the Altera timing constraints file (.sdc).	mikaeljf	5260d 14h	/versatile_mem_ctrl
20	Minor update of sdc-file.	mikaeljf	5262d 16h	/versatile_mem_ctrl
19	Added do-file for Modelsim waveform viewer.	mikaeljf	5268d 20h	/versatile_mem_ctrl
18	Updated the rtl/verilog Makefile and the bench Makefile.	mikaeljf	5269d 17h	/versatile_mem_ctrl
17	Modified rtl Makefile and tb_defines.v	mikaeljf	5272d 16h	/versatile_mem_ctrl