URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl] - Rev 55

Rev	Log message	Author	Age	Path
35	work for limited test case	unneback	5231d 11h	/versatile_mem_ctrl
34	added	unneback	5231d 11h	/versatile_mem_ctrl
33	work for limited test case, no cke inhibit for fifo empty	unneback	5231d 14h	/versatile_mem_ctrl
32	Updated the testbench to match the new wishbone interface.	mikaeljf	5234d 17h	/versatile_mem_ctrl
31	Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts.	mikaeljf	5236d 11h	/versatile_mem_ctrl
30	Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts.	mikaeljf	5236d 11h	/versatile_mem_ctrl
29	Adapted the test bench to the new wishbone interface.	mikaeljf	5240d 11h	/versatile_mem_ctrl
28	Fixed typos and updated the rtl Makefile and Altera-Modelsim script. Modified the counter-excel file and added missing module 'dff_sr.v'.	mikaeljf	5240d 13h	/versatile_mem_ctrl
27		unneback	5244d 04h	/versatile_mem_ctrl
26	compiles OK, not simulated	unneback	5246d 03h	/versatile_mem_ctrl