URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl] - Rev 59

Rev	Log message	Author	Age	Path
39	updated FIFO and SDR 16	unneback	5228d 05h	/versatile_mem_ctrl
38	casex in rw state to save logic	unneback	5230d 13h	/versatile_mem_ctrl
37		unneback	5231d 03h	/versatile_mem_ctrl
36		unneback	5231d 04h	/versatile_mem_ctrl
35	work for limited test case	unneback	5231d 11h	/versatile_mem_ctrl
34	added	unneback	5231d 11h	/versatile_mem_ctrl
33	work for limited test case, no cke inhibit for fifo empty	unneback	5231d 14h	/versatile_mem_ctrl
32	Updated the testbench to match the new wishbone interface.	mikaeljf	5234d 18h	/versatile_mem_ctrl
31	Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts.	mikaeljf	5236d 11h	/versatile_mem_ctrl
30	Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts.	mikaeljf	5236d 11h	/versatile_mem_ctrl