URL https://opencores.org/ocsvn/xulalx25soc/xulalx25soc/trunk

Subversion Repositories xulalx25soc

[/] [xulalx25soc/] [trunk] - Rev 87

Rev	Log message	Author	Age	Path
67	Simplifies logic, and guarantees that the minimum set value will always produce an int. For example, if the count was X before, setting X-1 wouldn't produce an interrupt since it had passed. Now it produces an interrupt, and keeps the next interrupt valid.	dgisselq	2960d 15h	/xulalx25soc/trunk
66	Simplified logic (barely).	dgisselq	2960d 15h	/xulalx25soc/trunk
65	Makes the auto-reload feature a parameterized (generic) feature, so the same code will work for both auto-reloadable and non-autoreloadable (i.e. watchdog) timers.	dgisselq	2960d 15h	/xulalx25soc/trunk
64	First (verified) working version.	dgisselq	2960d 15h	/xulalx25soc/trunk
63	Simplified logic.	dgisselq	2960d 15h	/xulalx25soc/trunk
62	Removed the pipe logic from the non-pipelined version, and made the NOOP a specific ALU instruction so that the PC is always properly updated.	dgisselq	2960d 15h	/xulalx25soc/trunk
61	Fixed the timing control wires: busy and valid will never both be true. Busy will be true (now) until valid is asserted, and busy will never not be asserted until valid is true.	dgisselq	2960d 15h	/xulalx25soc/trunk
60	LONG_MPY upgrade. This is part of swapping out the LDIHI instruction for a MPY, and the MPYS and MPYU instructions for MPYSHI and MPYUHI respectively.	dgisselq	2960d 15h	/xulalx25soc/trunk
59	Simplified logic.	dgisselq	2960d 15h	/xulalx25soc/trunk
58	Bug fix: the UART can now be reconfigured post-boot without a BREAK condition.	dgisselq	2960d 15h	/xulalx25soc/trunk