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[/] [zipcpu/] - Rev 90

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Rev	Log message	Author	Age	Path
70	Updated the assembler support files, zopcodes in particular, to handle the disassembly of the new very long instruction word codes.	dgisselq	3086d 08h	/zipcpu
69	This implements the "new Instruction Set" architecture for the Zip CPU. It's a massive change set, that touches just about everything but probably not enough of everything. Please see the spec.pdf for a description of this new architecture.	dgisselq	3092d 13h	/zipcpu
68	Updated specification, includes well illustrated pipeline discussion.	dgisselq	3127d 13h	/zipcpu
67	Includes timing diagrams in support of a very descriptive specification section.	dgisselq	3127d 13h	/zipcpu
66	Adjusted the support for the DEBUG_SCOPE within these so that it can be compiled in, or not, based upon an external build configuration file: cpudefs.v. That allows me to make that file project specific, while the rest of the CPU is shared among all projects.	dgisselq	3153d 13h	/zipcpu
65	Lots of logic simplifications to the core, in addition to better support for illegal instruction detection and bus error detection. The biggest change had to deal with pushing the debug write interface into the ALU write processing path. This simplifies the logic of adjusting the PC and CC registers primarily, but also any writes to other registers. It also delays these register writes by a clock, but since the debug interface is already ridiculously slow I doubt that matters any.	dgisselq	3153d 13h	/zipcpu
64	Shuffled some comments into here from elsewhere.	dgisselq	3153d 13h	/zipcpu
63	Simplified bus interactions, and added support for detecting illegal instructions (i.e. bus errors) in the pipefetch routine.	dgisselq	3153d 13h	/zipcpu
62	Simplified the subtraction logic, so the carry bit no longer depends on a separate 32-bit operation but becomes part of the subtract operation.	dgisselq	3153d 13h	/zipcpu
61	Simplified the bus delay logic. Depends upon the stall line being irrelevant outside of a bus cycle.	dgisselq	3153d 13h	/zipcpu

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