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[/] [zipcpu] - Rev 94

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Rev	Log message	Author	Age	Path
74	Added a bunch of debugging code to the Dhrystone benchmark assembly file, as well as two new testing assembly files.	dgisselq	3092d 18h	/zipcpu
73	Documentations updates.	dgisselq	3092d 19h	/zipcpu
72	Some updated graphics, now containing images of the CPU that include the divide and (currently non-existant) floating point unit.	dgisselq	3092d 19h	/zipcpu
71	This contains a bunch of bug fixes. (A lot ...) For example, the pipeline stall code has also seriously changed, to fixed the pipeline memory load/op stage conflict, while maintaining no-stall operation for operands that don't need an offset. This had a cascading effect, however, so that the multiply could no longer complete in a single cycle. Therefore, the timing on the multiplies was slowed down to two cycles from a single cycle. (It's the only two-cycle ALU operation ...) The illegal instruction code has also been fixed, so that illegal instructions no longer stalls the prefetch bus.	dgisselq	3092d 19h	/zipcpu
70	Updated the assembler support files, zopcodes in particular, to handle the disassembly of the new very long instruction word codes.	dgisselq	3092d 19h	/zipcpu
69	This implements the "new Instruction Set" architecture for the Zip CPU. It's a massive change set, that touches just about everything but probably not enough of everything. Please see the spec.pdf for a description of this new architecture.	dgisselq	3098d 23h	/zipcpu
68	Updated specification, includes well illustrated pipeline discussion.	dgisselq	3133d 23h	/zipcpu
67	Includes timing diagrams in support of a very descriptive specification section.	dgisselq	3134d 00h	/zipcpu
66	Adjusted the support for the DEBUG_SCOPE within these so that it can be compiled in, or not, based upon an external build configuration file: cpudefs.v. That allows me to make that file project specific, while the rest of the CPU is shared among all projects.	dgisselq	3159d 23h	/zipcpu
65	Lots of logic simplifications to the core, in addition to better support for illegal instruction detection and bus error detection. The biggest change had to deal with pushing the debug write interface into the ALU write processing path. This simplifies the logic of adjusting the PC and CC registers primarily, but also any writes to other registers. It also delays these register writes by a clock, but since the debug interface is already ridiculously slow I doubt that matters any.	dgisselq	3159d 23h	/zipcpu

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