OpenCores
URL https://opencores.org/ocsvn/r2000/r2000/trunk

Subversion Repositories r2000

[/] - Rev 32

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
12 To simplify the exception traitement: Instruction are executed serialy. ameziti 6031d 23h /
11 Exception event must be treated CONCURRENTLY with the other event that stall the pipeline. ameziti 6032d 00h /
10 Modification of the CP0. ameziti 6032d 00h /
9 When D-Cache miss, there's no need to stall MEMWB and freeze WB.
The solution is to flush MEMWB only.
ameziti 6032d 00h /
8 Enhancement of the "Controler specification doc". ameziti 6035d 00h /
7 Add Pipeline Controler specification documentation. ameziti 6035d 22h /
6 When D-Cache miss, there's no need to stall MEMWB and freeze WB.
The solution is to flush MEMWB only.
ameziti 6036d 00h /
5 Remove the Multiple Arithmetic Unit fonction.
- The Pipeline must stall when Mult/Div unit is busy.
- Whether there's a mflo or mfhi.
- see `define MULTIPLE_ALU
ameziti 6036d 22h /
4 Add Soc Image in the Specification documentation ameziti 6058d 00h /
3 This commit was manufactured by cvs2svn to create tag 'arelease'. 6059d 09h /

< Prev 1 2

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.