URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] - Rev 135

Rev	Log message	Author	Age	Path
135	prepared start of receiving if ren is not active.	simont	7749d 04h	/
134	fix bug in case execution of two data dependent instructions.	simont	7749d 04h	/
133	fix bug in substraction.	simont	7749d 07h	/
132	change branch instruction execution (reduse needed clock periods).	simont	7752d 22h	/
131	prepare programs for new timing.	simont	7752d 22h	/
130	prepared programs for new timing.	simont	7752d 22h	/
129	updated...	simont	7752d 22h	/
128	chance idat_ir to 24 bit wide	simont	7762d 05h	/
127	fix bug (cyc_o and stb_o)	simont	7762d 05h	/
126	define OC8051_XILINX_RAMB added	simont	7762d 05h	/
125	update, add prescaler, rclk, tclk.	simont	7762d 05h	/
124	add support for external rom from xilinx ramb4	simont	7762d 05h	/
123	fiz bug iv pcs operation.	simont	7764d 01h	/
122	deifne OC8051_ROM added	simont	7767d 05h	/
121	Change pc add value from 23'h to 16'h	simont	7767d 05h	/
120	defines for pherypherals added	simont	7768d 03h	/
119	remove signal sbuf_txd [12:11]	simont	7768d 06h	/
118	change wr_sft to 2 bit wire.	simont	7768d 23h	/
117	Register oc8051_sfr dato output, add signal wait_data.	simont	7768d 23h	/
116	change sfr's interface.	simont	7771d 00h	/