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Rev Log message Author Age Path
83 Cleaned up the code. No functional changes. mihad 7823d 19h /
82 This commit was manufactured by cvs2svn to create tag 'rel_5'. 7837d 15h /
81 Updated synchronization in top level fifo modules. mihad 7837d 15h /
80 This commit was manufactured by cvs2svn to create tag 'rel_4'. 7840d 20h /
79 Updated. mihad 7840d 20h /
78 Old files with wrong names removed. mihad 7840d 20h /
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7840d 20h /
76 TRDY output delay was 10 instead of 11. Repaired. mihad 7843d 20h /
75 Include statement moved out of off/on pragma as reported by Uwe. mihad 7846d 21h /
74 This commit was manufactured by cvs2svn to create tag 'rel_3'. 7846d 21h /
73 Bug fixes, testcases added. mihad 7846d 21h /
72 *** empty log message *** mihad 7894d 01h /
71 Changed the code a bit to make it more readable.
Functionality not changed in any way.
More robust synchronization in fifos is still pending.
mihad 7901d 16h /
70 This commit was manufactured by cvs2svn to create tag 'rel_2'. 7939d 00h /
69 Changed BIST signal names etc.. mihad 7939d 00h /
68 Changed wrong signal name scanb_sen into scanb_en. tadejm 7942d 09h /
67 Changed BIST signals for RAMs. tadejm 7942d 14h /
66 Changed empty status generation in pciw_fifo_control.v mihad 7946d 01h /
65 Cleaned up non-blocking assignments in combinatinal logic statements mihad 7948d 23h /
64 The testcase I just added in previous revision repaired mihad 7949d 01h /

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