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Rev Log message Author Age Path
66 dwm tw, bl paramter are passed on the wb2sdrc module dinesha 4393d 13h /
65 Updated Log file with CAS latency support 4,5 dinesha 4393d 21h /
64 CAS Latency support added for 4,5 dinesha 4393d 21h /
63 FPGA Bench mark results are added dinesha 4512d 20h /
62 Synthesis constraint for simplify dinesha 4512d 20h /
61 RTL file list are added into SVN dinesha 4512d 21h /
60 warning cleanup dinesha 4512d 21h /
59 Control path request and data are register now for better FPGA timing dinesha 4512d 21h /
58 Read Data is register on RD_FAST=0 case dinesha 4512d 21h /
57 Synthesis constraints are added dinesha 4513d 11h /
56 FPGA Synth optimisation dinesha 4513d 12h /
55 FPGA Synthesis timing optimisation dinesha 4513d 13h /
54 FPGA Timing Optimisation dinesha 4516d 10h /
53 Test bench upgradation dinesha 4517d 11h /
52 Documentation update for request control and transfer control block dinesha 4517d 11h /
51 FPGA relating timing optimisation done dinesha 4517d 11h /
50 Bug fix the request length is fixe dinesha 4519d 15h /
49 clean up dinesha 4520d 14h /
48 top-level cleanup dinesha 4520d 14h /
47 SDRAM bus converter bug fix and top-level signal clean up dinesha 4520d 14h /

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