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Rev Log message Author Age Path
30 Changed to xilinx specific RAM jesus 7953d 12h /
29 Fixed (IX/IY+d) timing and added all GB op-codes jesus 7953d 12h /
28 Adapted for zxgate jesus 7954d 12h /
27 Xilinx SSRAM, initial release jesus 7954d 12h /
26 Fixed instruction timing for POP and DJNZ jesus 7968d 04h /
25 IX/IY timing and ADC/SBC fix jesus 7969d 14h /
24 no message jesus 7975d 10h /
23 Fixed T2Write jesus 7975d 11h /
22 Added 8080 top level jesus 7975d 11h /
21 no message jesus 7980d 10h /
20 Updated for new T80s generic jesus 7980d 10h /
19 Initial version jesus 7980d 10h /
18 Added T2Write generic jesus 7980d 16h /
17 Removed write through jesus 7982d 09h /
16 no message jesus 7982d 13h /
15 Added clock enable and fixed IM 2 jesus 7989d 12h /
14 Changed to Xilinx ROM jesus 8009d 00h /
13 Initial import jesus 8009d 00h /
12 Initial import jesus 8009d 00h /
11 Added support for XST jesus 8009d 01h /

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