URL https://opencores.org/ocsvn/tv80/tv80/trunk

Subversion Repositories tv80

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Rev	Log message	Author	Age	Path
47	This commit was manufactured by cvs2svn to create branch 'restruc2'.		7155d 14h	/
46	This commit was manufactured by cvs2svn to create branch 'restruc1'.		7155d 14h	/
45	Added negedge version of top	ghutchis	7155d 14h	/
44	Updated run script for better dump control	ghutchis	7155d 17h	/
43	Fixed assembly routines for blk mem copy test	ghutchis	7178d 06h	/
42	Added decode of OUT (##),A instruction Removed dump-by-default and added DUMP_START define	ghutchis	7178d 06h	/
41	Added random-read value port	ghutchis	7180d 10h	/
40	Added random-read port and block memory instruction test	ghutchis	7180d 10h	/
39	Added checksum port definitions, and test for block-OUT instructions	ghutchis	7180d 11h	/
38	Added command-line options for help (-h) and run with instruction decode (-d)	ghutchis	7182d 04h	/
37	Added new I/O registers for testing block I/O	ghutchis	7182d 04h	/
36	Removed default instruction decode	ghutchis	7182d 04h	/
35	Updated IO registers to add checksum and increment-on-read registers used for testing block I/O instructions.	ghutchis	7182d 15h	/
34	Created test for block I/O instructions	ghutchis	7182d 15h	/
33	Added missing IncDec controls to OUTI/OUTD instructions	ghutchis	7183d 12h	/
32	Added "bintr" basic interrupt test, which tests Z80 interrupt mode 1.	ghutchis	7198d 14h	/
31	1) Added environment support for Z80 op decode in log file. 2) Fixed env support for interrupt generation and clearing	ghutchis	7198d 14h	/
30	Added HTML version of docs	ghutchis	7201d 14h	/
29	Added references	ghutchis	7201d 14h	/
28	Added code to initialize RAM to all 00 at environment start-up time.	ghutchis	7201d 14h	/

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Subversion Repositories tv80

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