OpenCores
URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] - Rev 32

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
32 Updated the testbench to match the new wishbone interface. mikaeljf 5235d 05h /
31 Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts. mikaeljf 5236d 22h /
30 Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts. mikaeljf 5236d 23h /
29 Adapted the test bench to the new wishbone interface. mikaeljf 5240d 23h /
28 Fixed typos and updated the rtl Makefile and Altera-Modelsim script. Modified the counter-excel file and added missing module 'dff_sr.v'. mikaeljf 5241d 00h /
27 unneback 5244d 16h /
26 compiles OK, not simulated unneback 5246d 15h /
25 unneback 5246d 18h /
24 Updated the memory controller according to recent update of Versatile_counter. Modified the rtl Makefile and added an excel file with counter definitions. mikaeljf 5247d 05h /
23 Removed redundant code. mikaeljf 5254d 22h /
22 Updated the Altera timing constraints file, also minor updates of defines file and Makefile. mikaeljf 5256d 18h /
21 Updated the Altera timing constraints file (.sdc). mikaeljf 5260d 21h /
20 Minor update of sdc-file. mikaeljf 5262d 22h /
19 Added do-file for Modelsim waveform viewer. mikaeljf 5269d 03h /
18 Updated the rtl/verilog Makefile and the bench Makefile. mikaeljf 5270d 00h /
17 Modified rtl Makefile and tb_defines.v mikaeljf 5272d 23h /
16 Added fizzim.pl mikaeljf 5272d 23h /
15 Added module 'dcm_pll.v' with Xilinx DCM and Altera altpll, also added module 'ddr_ff.v' with Xilinx IDDR/ODDR and Altera altddio_in/altddio_out. Added simple simulation script for Xilinx and Altera. Added simple synthesis script and SDC timing constraints for Altera. mikaeljf 5273d 23h /
14 Added external feedback of DDR SDRAM clock. mikaeljf 5364d 02h /
13 Modified DDR FSM for read and write, added counters for burst length, read/write latency, write recovery time etc. Added DCM with external feedback. mikaeljf 5364d 04h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.