OpenCores
URL https://opencores.org/ocsvn/virtex7_pcie_dma/virtex7_pcie_dma/trunk

Subversion Repositories virtex7_pcie_dma

[/] - Rev 45

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
45 Fixed duplicate driver and Vivado 2018.1 PCIe core fransschreuder 1886d 05h /
44 EDITED: added image size aborga 1973d 21h /
43 ADDED: README.md to be parsed by the OC project page aborga 1974d 02h /
42 Added filter in wuppercodegen in order to generate 2d arrays of registers fransschreuder 2319d 02h /
41 Added brief description of Wishbone broel 2419d 02h /
40 Updated comment header for syscon. broel 2419d 03h /
39 Added Wishbone bus to Wupper plus a Wishbone memory as an example. broel 2422d 22h /
38 Fixed include of stdint.h broel 2431d 05h /
37 * Added WupperCodeGen, a tool to generate the registermap vhdl, c++ and latex doc from a single .YAML file
* Fixed bug: crash when polling enable bits while transferring DMA in two directions at the same time
* Code cleanup
* Updated documentation with WupperCodeGen		 fransschreuder 2431d 21h /
36 Updated documentation fransschreuder 2766d 22h /
35 FIXED:
* PCIe lock when reading registers on a high frequency
* Added threshold registers for Prog Full of the FromHost fifo
* Code cleanup		 fransschreuder 2821d 03h /
34 FIXED:
* Wrong TLP length reported on register writes
* Two simultaneous interrupts were not handled
* XADC wizard for ultrascale devices

Added:
* Added voltage (int, aux, bram) readout on XADC wizards		 fransschreuder 2926d 22h /
33 ADDED:
-- supportedtools.tex, again to test the OC repo		 aborga 2971d 21h /
32 MODIFIED:
-- minor things just to test OC svn repo		 aborga 2971d 21h /
31 Added example application documentation. oussamak 3065d 22h /
30 Added:
* Wupper GUI with speed test and chain test
* Added wupper-dma-transfer, wupper-chaintest and wupper-write
* Several bug fixes in the Wupper tools		 oussamak 3065d 23h /
29 Improved application to reflect both up and down transfers fransschreuder 3107d 21h /
28 Added registermap reset fransschreuder 3107d 23h /
27 Fixed:
* BUG 2580: Missing packets in receive (PC => FPGA) path

Changed:
* Client tags now handled by Xilinx IP core
* fifo signals to reflect upfifo and downfifo naming		 fransschreuder 3108d 02h /
26 Added sys_clk constraint fransschreuder 3108d 04h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.