OpenCores
URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_12/] [bench/] [verilog/] - Rev 186

Rev

Filtering Options

Clear current filter

Rev Log message Author Age Path
186 root 5614d 22h /8051/tags/rel_12/bench/verilog/
185 root 5670d 23h /8051/tags/rel_12/bench/verilog/
182 This commit was manufactured by cvs2svn to create tag 'rel_12'. 7749d 15h /8051/tags/rel_12/bench/verilog/
167 add readmem for ea. simont 7775d 02h /8051/tags/rel_12/bench/verilog/
166 Change test monitor from ports to external data memory. simont 7775d 20h /8051/tags/rel_12/bench/verilog/
165 remove dumpvars. simont 7776d 00h /8051/tags/rel_12/bench/verilog/
157 change data output. simont 7776d 02h /8051/tags/rel_12/bench/verilog/
156 add FREQ paremeter. simont 7776d 02h /8051/tags/rel_12/bench/verilog/
125 update, add prescaler, rclk, tclk. simont 7826d 03h /8051/tags/rel_12/bench/verilog/
124 add support for external rom from xilinx ramb4 simont 7826d 03h /8051/tags/rel_12/bench/verilog/
120 defines for pherypherals added simont 7832d 00h /8051/tags/rel_12/bench/verilog/
111 Remove instruction cache and wb_interface simont 7838d 18h /8051/tags/rel_12/bench/verilog/
103 rename signals simont 7839d 22h /8051/tags/rel_12/bench/verilog/
97 initial inport simont 7840d 01h /8051/tags/rel_12/bench/verilog/
84 remove wb_bus_mon simont 7918d 22h /8051/tags/rel_12/bench/verilog/
74 add module oc8051_wb_iinterface simont 7995d 20h /8051/tags/rel_12/bench/verilog/
68 add instruction cache and DELAY parameters for external ram, rom simont 7999d 23h /8051/tags/rel_12/bench/verilog/
59 add external rom simont 8006d 18h /8051/tags/rel_12/bench/verilog/
46 prepared header simont 8023d 19h /8051/tags/rel_12/bench/verilog/
37 added signals ack, stb and cyc simont 8050d 22h /8051/tags/rel_12/bench/verilog/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.