URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_12/] [rtl/] [verilog/] - Rev 186

Rev	Log message	Author	Age	Path
186		root	5534d 08h	/8051/tags/rel_12/rtl/verilog/
185		root	5590d 09h	/8051/tags/rel_12/rtl/verilog/
182	This commit was manufactured by cvs2svn to create tag 'rel_12'.		7669d 01h	/8051/tags/rel_12/rtl/verilog/
181	Simulation reports added.	simont	7669d 01h	/8051/tags/rel_12/rtl/verilog/
179	add /* synopsys xx_case */ to case statments.	simont	7669d 02h	/8051/tags/rel_12/rtl/verilog/
178	x replaced with 0.	simont	7669d 04h	/8051/tags/rel_12/rtl/verilog/
177	Fix bug in case of writing and reading from same address.	simont	7680d 07h	/8051/tags/rel_12/rtl/verilog/
175	initial inport.	simont	7680d 09h	/8051/tags/rel_12/rtl/verilog/
174	ram modules added.	simont	7680d 09h	/8051/tags/rel_12/rtl/verilog/
173	simualtion `ifdef added	simont	7680d 09h	/8051/tags/rel_12/rtl/verilog/
172	BIST signals added.	simont	7683d 09h	/8051/tags/rel_12/rtl/verilog/
171	fix bug in DA operation.	simont	7691d 06h	/8051/tags/rel_12/rtl/verilog/
158	fix bug.	simont	7695d 12h	/8051/tags/rel_12/rtl/verilog/
153	`ifdef added.	simont	7697d 06h	/8051/tags/rel_12/rtl/verilog/
152	sub_result output added.	simont	7697d 06h	/8051/tags/rel_12/rtl/verilog/
151	remove pc_r register.	simont	7697d 06h	/8051/tags/rel_12/rtl/verilog/
150	fix some bugs.	simont	7697d 06h	/8051/tags/rel_12/rtl/verilog/
149	pipelined acces to axternal instruction interface added.	simont	7697d 06h	/8051/tags/rel_12/rtl/verilog/
148	include "8051_defines" added.	simont	7697d 06h	/8051/tags/rel_12/rtl/verilog/
146	fix bug in movc intruction.	simont	7719d 06h	/8051/tags/rel_12/rtl/verilog/