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Rev Log message Author Age Path
117 Tristate signal tx_o is separated to tx_o and tx_oen_o. Both signals need
to be joined together on higher level.		 mohor 7636d 12h /can/tags/asyst_2/
115 Artisan ram instances added. simons 7642d 06h /can/tags/asyst_2/
112 Tx and rx length are limited to 8 bytes regardless to the DLC value. tadejm 7669d 07h /can/tags/asyst_2/
111 Fixed according to the linter.
Case statement for data_out joined.		 mohor 7671d 07h /can/tags/asyst_2/
110 Fixed according to the linter. mohor 7671d 07h /can/tags/asyst_2/
109 Fixed according to the linter. mohor 7671d 08h /can/tags/asyst_2/
108 Fixed according to the linter. mohor 7671d 09h /can/tags/asyst_2/
107 Fixed according to the linter. mohor 7671d 09h /can/tags/asyst_2/
106 Unused signal removed. mohor 7677d 07h /can/tags/asyst_2/
104 Synchronization fixed. In some strange cases it didn't work according to
the VHDL reference model.		 tadejm 7677d 20h /can/tags/asyst_2/
102 Little fixes (to fix warnings). mohor 7680d 11h /can/tags/asyst_2/
100 Synchronization changed. mohor 7684d 13h /can/tags/asyst_2/
99 PCI_BIST replaced with CAN_BIST. mohor 7684d 13h /can/tags/asyst_2/
97 Overrun fifo implemented with FFs, because it is not possible to create such a memory. simons 7690d 00h /can/tags/asyst_2/
95 Virtual silicon ram instances added. simons 7690d 01h /can/tags/asyst_2/
93 synthesis full_case parallel_case fixed. mohor 7695d 13h /can/tags/asyst_2/
92 clkout is clk/2 after the reset. mohor 7695d 21h /can/tags/asyst_2/
90 paralel_case and full_case compiler directives added to case statements. mohor 7696d 10h /can/tags/asyst_2/
88 Previous change removed. When resynchronization occurs we go to seg1
stage. sync stage does not cause another start of seg1 stage.		 mohor 7697d 08h /can/tags/asyst_2/
87 When hard_sync or resync occure we need to go to seg1 segment. Going to
sync segment is in that case blocked.		 mohor 7697d 08h /can/tags/asyst_2/

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