URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_21/] [bench/] - Rev 121

Rev	Log message	Author	Age	Path
121	Port signals are all set to zero after reset.	mohor	7476d 15h	/dbg_interface/tags/rel_21/bench/
120	test stall_test added.	mohor	7476d 17h	/dbg_interface/tags/rel_21/bench/
117	Define name changed.	mohor	7478d 14h	/dbg_interface/tags/rel_21/bench/
116	Data latching changed when testing WB.	mohor	7478d 14h	/dbg_interface/tags/rel_21/bench/
115	More debug data added.	mohor	7478d 18h	/dbg_interface/tags/rel_21/bench/
114	CRC generation iand verification in bench changed.	mohor	7478d 19h	/dbg_interface/tags/rel_21/bench/
113	IDCODE test improved.	mohor	7478d 21h	/dbg_interface/tags/rel_21/bench/
112	dbg_tb_defines.v not used.	mohor	7479d 15h	/dbg_interface/tags/rel_21/bench/
111	Define tap_defines.v added to test bench.	mohor	7479d 15h	/dbg_interface/tags/rel_21/bench/
110	Waiting for "ready" improved.	mohor	7479d 16h	/dbg_interface/tags/rel_21/bench/
102	New version.	mohor	7481d 11h	/dbg_interface/tags/rel_21/bench/
101	Almost finished.	mohor	7481d 12h	/dbg_interface/tags/rel_21/bench/
99	cpu registers added.	mohor	7482d 14h	/dbg_interface/tags/rel_21/bench/
96	Working.	mohor	7483d 18h	/dbg_interface/tags/rel_21/bench/
95	Temp version.	mohor	7484d 06h	/dbg_interface/tags/rel_21/bench/
93	tmp version.	mohor	7485d 17h	/dbg_interface/tags/rel_21/bench/
92	temp version.	mohor	7488d 21h	/dbg_interface/tags/rel_21/bench/
91	tmp version.	mohor	7489d 16h	/dbg_interface/tags/rel_21/bench/
90	tmp version.	mohor	7490d 11h	/dbg_interface/tags/rel_21/bench/
89	temp4 version.	mohor	7491d 17h	/dbg_interface/tags/rel_21/bench/