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[/] [dbg_interface/] [tags/] [rel_8/] - Rev 32

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Rev Log message Author Age Path
32 Stupid bug that was entered by previous update fixed. mohor 8180d 04h /dbg_interface/tags/rel_8/
31 trst synchronization is not needed and was removed. mohor 8180d 05h /dbg_interface/tags/rel_8/
30 IDCODE bug fixed, chains reused to decreas size of core. Data is shifted-in
not filled-in. Tested in hw.		 mohor 8191d 10h /dbg_interface/tags/rel_8/
29 Document revised and put tp better form. mohor 8194d 22h /dbg_interface/tags/rel_8/
28 TDO and TDO Enable signal are separated into two signals. mohor 8227d 06h /dbg_interface/tags/rel_8/
27 Warnings from synthesys tools fixed. mohor 8241d 07h /dbg_interface/tags/rel_8/
26 Warnings from synthesys tools fixed. mohor 8241d 07h /dbg_interface/tags/rel_8/
25 trst signal is synchronized to wb_clk_i. mohor 8242d 04h /dbg_interface/tags/rel_8/
24 CRC changed so more thorough testing is done. mohor 8243d 06h /dbg_interface/tags/rel_8/
23 Trace disabled by default. mohor 8249d 08h /dbg_interface/tags/rel_8/
22 Register length fixed. mohor 8249d 08h /dbg_interface/tags/rel_8/
21 CRC is returned when chain selection data is transmitted. mohor 8250d 04h /dbg_interface/tags/rel_8/
20 Crc generation is different for read or write commands. Small synthesys fixes. mohor 8251d 07h /dbg_interface/tags/rel_8/
19 Wishbone data latched on wb_clk_i instead of risc_clk. mohor 8263d 07h /dbg_interface/tags/rel_8/
18 Reset signals are not combined any more. mohor 8265d 16h /dbg_interface/tags/rel_8/
17 dbg_timescale.v changed to timescale.v This is done for the simulation of
few different cores in a single project.		 mohor 8289d 06h /dbg_interface/tags/rel_8/
16 bs_chain_o port added. mohor 8291d 06h /dbg_interface/tags/rel_8/
15 bs_chain_o added. mohor 8291d 07h /dbg_interface/tags/rel_8/
14 Document updated. mohor 8292d 04h /dbg_interface/tags/rel_8/
13 Signal names changed to lowercase. mohor 8292d 07h /dbg_interface/tags/rel_8/

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