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[/] [dbg_interface/] [tags/] [rev_23/] - Rev 24

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Rev Log message Author Age Path
24 CRC changed so more thorough testing is done. mohor 8275d 02h /dbg_interface/tags/rev_23/
23 Trace disabled by default. mohor 8281d 05h /dbg_interface/tags/rev_23/
22 Register length fixed. mohor 8281d 05h /dbg_interface/tags/rev_23/
21 CRC is returned when chain selection data is transmitted. mohor 8282d 01h /dbg_interface/tags/rev_23/
20 Crc generation is different for read or write commands. Small synthesys fixes. mohor 8283d 03h /dbg_interface/tags/rev_23/
19 Wishbone data latched on wb_clk_i instead of risc_clk. mohor 8295d 04h /dbg_interface/tags/rev_23/
18 Reset signals are not combined any more. mohor 8297d 13h /dbg_interface/tags/rev_23/
17 dbg_timescale.v changed to timescale.v This is done for the simulation of
few different cores in a single project.		 mohor 8321d 03h /dbg_interface/tags/rev_23/
16 bs_chain_o port added. mohor 8323d 02h /dbg_interface/tags/rev_23/
15 bs_chain_o added. mohor 8323d 04h /dbg_interface/tags/rev_23/
14 Document updated. mohor 8324d 01h /dbg_interface/tags/rev_23/
13 Signal names changed to lowercase. mohor 8324d 04h /dbg_interface/tags/rev_23/
12 Wishbone interface added, few fixes for better performance,
hooks for boundary scan testing added.		 mohor 8325d 04h /dbg_interface/tags/rev_23/
11 Changes connected to the OpenRISC access (SPR read, SPR write). mohor 8346d 00h /dbg_interface/tags/rev_23/
10 First official release 1.0. mohor 8350d 04h /dbg_interface/tags/rev_23/
9 Working version. Few bugs fixed, comments added. mohor 8350d 04h /dbg_interface/tags/rev_23/
8 Asynchronous set/reset not used in trace any more. mohor 8351d 02h /dbg_interface/tags/rev_23/
7 First official release 1.0. mohor 8351d 02h /dbg_interface/tags/rev_23/
6 Minor changes for simulation. mohor 8351d 02h /dbg_interface/tags/rev_23/
5 Trace fixed. Some registers changed, trace simplified. mohor 8352d 00h /dbg_interface/tags/rev_23/

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