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[/] [ethmac/] [branches/] [unneback/] [rtl/] [verilog/] - Rev 317

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Rev Log message Author Age Path
317 Multicast detection fixed. Only the LSB of the first byte is checked. igorm 7388d 06h /ethmac/branches/unneback/rtl/verilog/
312 Corrected address mismatch for xilinx RAMB4_S8 model which has wider address than RAMB4_S16. tadejm 7491d 02h /ethmac/branches/unneback/rtl/verilog/
306 Lapsus fixed (!we -> ~we). simons 7492d 00h /ethmac/branches/unneback/rtl/verilog/
304 WISHBONE slave changed and tested from only 32-bit accesss to byte access. tadejm 7513d 21h /ethmac/branches/unneback/rtl/verilog/
302 mbist signals updated according to newest convention markom 7540d 07h /ethmac/branches/unneback/rtl/verilog/
301 Update RxEnSync only when mrxdv_pad_i is inactive (LOW). knguyen 7550d 23h /ethmac/branches/unneback/rtl/verilog/
297 Artisan ram instance added. simons 7603d 22h /ethmac/branches/unneback/rtl/verilog/
288 This file was not part of the RTL before, but it should be here. simons 7640d 00h /ethmac/branches/unneback/rtl/verilog/
286 Define file in eth_cop.v is changed to eth_defines.v. Some defines were
moved from tb_eth_defines.v to eth_defines.v.		 mohor 7666d 03h /ethmac/branches/unneback/rtl/verilog/
285 Binary operator used instead of unary (xnor). mohor 7666d 04h /ethmac/branches/unneback/rtl/verilog/
284 Busy was set 2 cycles too late. Reported by Dennis Scott. mohor 7694d 05h /ethmac/branches/unneback/rtl/verilog/
283 RxBDAddress was updated also when value to r_TxBDNum was written with
greater value than allowed.		 mohor 7721d 23h /ethmac/branches/unneback/rtl/verilog/
280 Reset has priority in some flipflops. mohor 7800d 00h /ethmac/branches/unneback/rtl/verilog/
278 A new bug (entered with previous update) fixed. When abort occured sometimes
data transmission was blocked.		 mohor 7800d 01h /ethmac/branches/unneback/rtl/verilog/
277 When padding was enabled and crc disabled, frame was not ended correctly. mohor 7800d 02h /ethmac/branches/unneback/rtl/verilog/
276 Defer indication changed. tadejm 7800d 02h /ethmac/branches/unneback/rtl/verilog/
275 Fix MTxErr or prevent sending too big frames. mohor 7807d 06h /ethmac/branches/unneback/rtl/verilog/
272 When control packets were received, they were ignored in some cases. tadejm 7808d 01h /ethmac/branches/unneback/rtl/verilog/
270 When receiving normal data frame and RxFlow control was switched on, RXB
interrupt was not set.		 mohor 7809d 03h /ethmac/branches/unneback/rtl/verilog/
269 When in full duplex, transmit was sometimes blocked. Fixed. mohor 7810d 03h /ethmac/branches/unneback/rtl/verilog/

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