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Rev Log message Author Age Path
180 Bench outputs data to display every 128 bytes. mohor 7948d 00h /ethmac/tags/rel_17/bench/verilog/
179 Beautiful tests merget together mohor 7948d 01h /ethmac/tags/rel_17/bench/verilog/
178 Rearanged testcases mohor 7948d 01h /ethmac/tags/rel_17/bench/verilog/
177 Bug in MIIM fixed. mohor 7948d 04h /ethmac/tags/rel_17/bench/verilog/
170 Headers changed. mohor 7948d 07h /ethmac/tags/rel_17/bench/verilog/
169 New testbench. Thanks to Tadej M - "The Spammer". mohor 7948d 07h /ethmac/tags/rel_17/bench/verilog/
158 Typo fixed. mohor 7953d 03h /ethmac/tags/rel_17/bench/verilog/
157 This testbench will soon be obsolete. Please use tb_ethernet.v mohor 7955d 08h /ethmac/tags/rel_17/bench/verilog/
156 Valid testbench. mohor 7955d 08h /ethmac/tags/rel_17/bench/verilog/
155 Minor changes. mohor 7955d 08h /ethmac/tags/rel_17/bench/verilog/
124 Define ETH_MIIMODER_RST corrected to 0x00000400. mohor 7998d 02h /ethmac/tags/rel_17/bench/verilog/
121 gsr added for use when ETH_XILINX_RAMB4 define is set. mohor 8000d 03h /ethmac/tags/rel_17/bench/verilog/
117 Clock mrx_clk set to 2.5 MHz. mohor 8004d 05h /ethmac/tags/rel_17/bench/verilog/
116 Testing environment also includes traffic cop, memory interface and host
interface.		 mohor 8004d 05h /ethmac/tags/rel_17/bench/verilog/
108 Testbench supports unaligned accesses. mohor 8081d 09h /ethmac/tags/rel_17/bench/verilog/
107 TX_BUF_BASE changed. mohor 8081d 09h /ethmac/tags/rel_17/bench/verilog/
92 Some defines that are used in testbench only were moved to tb_eth_defines.v
file.		 mohor 8126d 06h /ethmac/tags/rel_17/bench/verilog/
80 Small fixes for external/internal DMA missmatches. mohor 8147d 02h /ethmac/tags/rel_17/bench/verilog/
67 EXTERNAL_DMA used instead of WISHBONE_DMA. mohor 8157d 06h /ethmac/tags/rel_17/bench/verilog/
66 Testbench fixed, code simplified, unused signals removed. mohor 8157d 12h /ethmac/tags/rel_17/bench/verilog/

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