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Rev Log message Author Age Path
238 Defines fixed to use generic RAM by default. mohor 7888d 20h /ethmac/tags/rel_19/
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7891d 02h /ethmac/tags/rel_19/
235 rev 4. mohor 7891d 16h /ethmac/tags/rel_19/
234 Figure list assed to the revision 3. mohor 7892d 00h /ethmac/tags/rel_19/
233 Revision 0.3 released. Some figures added. mohor 7892d 01h /ethmac/tags/rel_19/
232 fpga define added. mohor 7896d 20h /ethmac/tags/rel_19/
231 Description of Core Modules added (figure). mohor 7898d 21h /ethmac/tags/rel_19/
229 case changed to casex. mohor 7902d 18h /ethmac/tags/rel_19/
227 Changed BIST scan signals. tadejm 7902d 22h /ethmac/tags/rel_19/
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7902d 23h /ethmac/tags/rel_19/
225 Some minor changes. tadejm 7902d 23h /ethmac/tags/rel_19/
224 Signals for a wave window in Modelsim. tadejm 7903d 00h /ethmac/tags/rel_19/
223 Some code changed due to bug fixes. tadejm 7903d 01h /ethmac/tags/rel_19/
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.		 mohor 7906d 23h /ethmac/tags/rel_19/
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.		 mohor 7909d 23h /ethmac/tags/rel_19/
218 Typo error fixed. (When using Bist) mohor 7910d 01h /ethmac/tags/rel_19/
217 Bist supported. mohor 7910d 01h /ethmac/tags/rel_19/
216 Bist signals added. mohor 7910d 01h /ethmac/tags/rel_19/
215 Bist supported. mohor 7910d 02h /ethmac/tags/rel_19/
214 Signals for WISHBONE B3 compliant interface added. mohor 7910d 22h /ethmac/tags/rel_19/

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