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[/] [ethmac/] [trunk/] [rtl/] - Rev 125

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Rev Log message Author Age Path
125 RxAbort changed. Packets received with MRxErr (from PHY) are also
aborted.		 mohor 8003d 02h /ethmac/trunk/rtl/
122 ethernet spram added. So far a generic ram and xilinx RAMB4 are used. mohor 8005d 03h /ethmac/trunk/rtl/
120 Unused files removed. mohor 8005d 04h /ethmac/trunk/rtl/
119 Ram , used for BDs changed from generic_spram to eth_spram_256x32. mohor 8005d 04h /ethmac/trunk/rtl/
118 ShiftEnded synchronization changed. mohor 8008d 19h /ethmac/trunk/rtl/
115 RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset. mohor 8010d 04h /ethmac/trunk/rtl/
114 EXTERNAL_DMA removed. External DMA not supported. mohor 8011d 01h /ethmac/trunk/rtl/
113 RxPointer bug fixed. mohor 8017d 17h /ethmac/trunk/rtl/
112 Previous bug wasn't succesfully removed. Now fixed. mohor 8018d 07h /ethmac/trunk/rtl/
111 Master state machine had a bug when switching from master write to
master read.		 mohor 8018d 20h /ethmac/trunk/rtl/
110 m_wb_cyc_o signal released after every single transfer. mohor 8018d 23h /ethmac/trunk/rtl/
109 Comment removed. mohor 8019d 00h /ethmac/trunk/rtl/
106 Outputs registered. Reset changed for eth_wishbone module. mohor 8086d 10h /ethmac/trunk/rtl/
105 Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
bug fixed.		 mohor 8095d 11h /ethmac/trunk/rtl/
104 FCS should not be included in NibbleMinFl. mohor 8097d 05h /ethmac/trunk/rtl/
103 Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is
selected in eth_defines.v		 mohor 8097d 06h /ethmac/trunk/rtl/
102 Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled
or not.		 mohor 8097d 06h /ethmac/trunk/rtl/
101 Short frame and ReceivedLengthOK were not detected correctly. mohor 8097d 06h /ethmac/trunk/rtl/
100 Generic ram or Xilinx ram can be used in fifo (selectable by setting
ETH_FIFO_XILINX in eth_defines.v).		 mohor 8097d 06h /ethmac/trunk/rtl/
97 Small typo fixed. lampret 8121d 04h /ethmac/trunk/rtl/

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