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[/] [minimips_superscalar/] [tags/] - Rev 38

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Rev Log message Author Age Path
37 pc update. mcafruni 1526d 04h /minimips_superscalar/tags/
36 update pc mcafruni 1526d 04h /minimips_superscalar/tags/
35 New delay_gate.vhd mcafruni 1529d 00h /minimips_superscalar/tags/
34 Delete delay_gate to upload a new one. mcafruni 1529d 00h /minimips_superscalar/tags/
33 New syscop.vhd mcafruni 1529d 00h /minimips_superscalar/tags/
32 Delete syscop to upload a new one. mcafruni 1529d 00h /minimips_superscalar/tags/
31 New top module. mcafruni 1529d 00h /minimips_superscalar/tags/
30 Delete top module to upload a new one. mcafruni 1529d 00h /minimips_superscalar/tags/
29 New banc register file. mcafruni 1529d 00h /minimips_superscalar/tags/
28 Delete banc.vhd to upload a new one. mcafruni 1529d 00h /minimips_superscalar/tags/
27 New bench on P1 tag. mcafruni 1529d 00h /minimips_superscalar/tags/
26 Delete bench to upload a new one. mcafruni 1529d 00h /minimips_superscalar/tags/
23 Moving the benchmarks folder into the trunk folder. mcafruni 1534d 18h /minimips_superscalar/tags/
22 Wrong code. (fi0.bin) But revealed a bug that needs attention. mcafruni 1534d 18h /minimips_superscalar/tags/
21 Correcting codes that work in behavioral simulation but cause problems with implementation. There must be more to be corrected yet. In analysis ... mcafruni 1534d 18h /minimips_superscalar/tags/
19 mcafruni 1902d 23h /minimips_superscalar/tags/
18 clock_gate.vhd: removed.
minimips.vhd: Clock2 input is wrongly connected to the clock signal (Do not ask me how that happened. I'm sorry.). The right thing is to be connected to the clock2 signal. Adjusted.		 mcafruni 1902d 23h /minimips_superscalar/tags/
16 FIR filter with 36 coefficients. (binary to run) mcafruni 1936d 08h /minimips_superscalar/tags/
15 FIR filter with 36 coefficients. mcafruni 1936d 08h /minimips_superscalar/tags/
14 Buble Sort algorithm. Four totally disorderly numbers are sorted in ascending order. Worst performance algorithm. mcafruni 1940d 03h /minimips_superscalar/tags/

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