OpenCores
URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [tags/] [Release_1.3/] - Rev 55

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
55 updated resource usage in comments JonasDC 4165d 08h /mod_sim_exp/tags/Release_1.3/
54 generic fifo design: correctrly inferred by xilinx and altera JonasDC 4165d 09h /mod_sim_exp/tags/Release_1.3/
53 correctly inferred ram for altera dual port ram JonasDC 4165d 15h /mod_sim_exp/tags/Release_1.3/
52 correct inferring of blockram, no additional resources. JonasDC 4165d 16h /mod_sim_exp/tags/Release_1.3/
51 true dual port ram for xilinx JonasDC 4165d 16h /mod_sim_exp/tags/Release_1.3/
50 added folder for ram descriptions
added experimental simple dual port ram implementation for xilinx		 JonasDC 4165d 16h /mod_sim_exp/tags/Release_1.3/
47 added documentation for the IP core. JonasDC 4245d 16h /mod_sim_exp/tags/Release_1.3/
46 chance run_auto port or mod_sim_exp_core to exp_m JonasDC 4245d 16h /mod_sim_exp/tags/Release_1.3/
45 chance run_auto port or mod_sim_exp_core to exp_m JonasDC 4245d 16h /mod_sim_exp/tags/Release_1.3/
44 toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface JonasDC 4249d 10h /mod_sim_exp/tags/Release_1.3/
43 made the core parameters generics JonasDC 4249d 10h /mod_sim_exp/tags/Release_1.3/
42 corrected wrong library name for mod_sim_exp_pkg JonasDC 4255d 18h /mod_sim_exp/tags/Release_1.3/
41 removed deprecated files from version control JonasDC 4255d 18h /mod_sim_exp/tags/Release_1.3/
40 adjusted core instantiation to new core module name JonasDC 4263d 22h /mod_sim_exp/tags/Release_1.3/
39 changed files to remove warnings from synthesis
last cell logic is simplified because of redundant logic		 JonasDC 4264d 09h /mod_sim_exp/tags/Release_1.3/
38 deprecated design files because of new pipeline structure, will be removed shortly JonasDC 4264d 14h /mod_sim_exp/tags/Release_1.3/
37 changed names of some generics of the multiplier.
moved the parameters for the core to the package of the core
testbench now uses this parameters to adapt to different bit widths

and new systolic pipeline now supports split or single pipeline		 JonasDC 4268d 11h /mod_sim_exp/tags/Release_1.3/
36 found bug in new pipeline structure, now working properly. (tested in sim)
mod_sim_exp_core uses new flexible pipeline as default.		 JonasDC 4269d 08h /mod_sim_exp/tags/Release_1.3/
35 new test values, 1st exponentiation gives error on result with new pipeline
commit for test purposes		 JonasDC 4269d 10h /mod_sim_exp/tags/Release_1.3/
34 operand memory now supports custom operand widths, the internal memory stays the fixed 1536 bit, but the bus width is now adjustable to any size below. JonasDC 4269d 11h /mod_sim_exp/tags/Release_1.3/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.