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[/] [mod_sim_exp/] [tags/] [Release_1.3/] [rtl/] [vhdl/] - Rev 87

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Rev	Log message	Author	Age	Path
79	Tag for version 1.3 (with new ram style	JonasDC	4102d 11h	/mod_sim_exp/tags/Release_1.3/rtl/vhdl/
77	found fault in code, now synthesizes normally	JonasDC	4108d 08h	/mod_sim_exp/tags/Release_1.3/rtl/vhdl/
75	made rw_address a vector of a fixed width	JonasDC	4110d 19h	/mod_sim_exp/tags/Release_1.3/rtl/vhdl/
74	removed C_NR_OP and C_NR_M from the generic of mod_sim_exp_core and made them contstants, because currently no other values than 4 an 2 resp. are supported/can be implemented.	JonasDC	4113d 16h	/mod_sim_exp/tags/Release_1.3/rtl/vhdl/
73	updated plb interface, mem_style and device generics added	JonasDC	4114d 15h	/mod_sim_exp/tags/Release_1.3/rtl/vhdl/
69	big update, the mod_sim_exp core now has a selectable ram structure. a generic ram that should be usable in any fpga, a asymmetric ram that is usable for some devices of altera or xilinx and uses less resources.	JonasDC	4115d 15h	/mod_sim_exp/tags/Release_1.3/rtl/vhdl/
67	added memory modules for modulus and operands for FPGA's that support asymmetric memory inferring.	JonasDC	4115d 18h	/mod_sim_exp/tags/Release_1.3/rtl/vhdl/
66	added asymmetric ram structures to support a more performant ramstyle. defined for xilinx and altera, not tested with other tools.	JonasDC	4115d 18h	/mod_sim_exp/tags/Release_1.3/rtl/vhdl/
65	updated plb interface, now modulus is selectable and, fifo depth is adjustable. updated makefile with new sources and update component in package	JonasDC	4123d 10h	/mod_sim_exp/tags/Release_1.3/rtl/vhdl/
63	now using a generic description of the ram for the memory. the core now should synthesize for al fpga's, no device specific code anymore. tested and synthesizes for altera and xilinx	JonasDC	4123d 15h	/mod_sim_exp/tags/Release_1.3/rtl/vhdl/
62	not used anymore	JonasDC	4123d 18h	/mod_sim_exp/tags/Release_1.3/rtl/vhdl/
61	updated comments, added optional altera constraint	JonasDC	4123d 18h	/mod_sim_exp/tags/Release_1.3/rtl/vhdl/
60	generic version of the fifo, not device specific anymore, uses dpram_generic updated comments of RAM templates.	JonasDC	4126d 09h	/mod_sim_exp/tags/Release_1.3/rtl/vhdl/
59	added templates that correctly infer RAM, for dual port en true dual port RAM added general functions file, (used in the two RAM templates)	JonasDC	4126d 09h	/mod_sim_exp/tags/Release_1.3/rtl/vhdl/
55	updated resource usage in comments	JonasDC	4130d 08h	/mod_sim_exp/tags/Release_1.3/rtl/vhdl/
54	generic fifo design: correctrly inferred by xilinx and altera	JonasDC	4130d 09h	/mod_sim_exp/tags/Release_1.3/rtl/vhdl/
53	correctly inferred ram for altera dual port ram	JonasDC	4130d 15h	/mod_sim_exp/tags/Release_1.3/rtl/vhdl/
52	correct inferring of blockram, no additional resources.	JonasDC	4130d 16h	/mod_sim_exp/tags/Release_1.3/rtl/vhdl/
51	true dual port ram for xilinx	JonasDC	4130d 16h	/mod_sim_exp/tags/Release_1.3/rtl/vhdl/
50	added folder for ram descriptions added experimental simple dual port ram implementation for xilinx	JonasDC	4130d 16h	/mod_sim_exp/tags/Release_1.3/rtl/vhdl/

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Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [tags/] [Release_1.3/] [rtl/] [vhdl/] - Rev 87

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