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[/] [open8_urisc/] [trunk/] [VHDL/] - Rev 183

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Rev Log message Author Age Path
183 Renamed core to o8_cpu to match new naming scheme jshamlet 1582d 23h /open8_urisc/trunk/VHDL/
182 Simplified the address generation logic at the expense of making LDX take one additional clock cycle. This allowed the address logic to be split out of the main state machine and simplified (greatly). During this process, a bug in SDO was found and fixed that caused it to return through the wrong pipe fill state wnen auto increment was disabled. jshamlet 1582d 23h /open8_urisc/trunk/VHDL/
181 Altered the RSP instruction to allow the stack pointed to either be restored from registers or stored to registers based on the status of a processor bit. Also modified LDX to simplify the address logic. jshamlet 1583d 20h /open8_urisc/trunk/VHDL/
180 Added additional Open8 compatible modules jshamlet 1587d 23h /open8_urisc/trunk/VHDL/
177 Fixed comments in RTC module jshamlet 2908d 00h /open8_urisc/trunk/VHDL/
176 Fixed documentation errors,
Modified uSec_Tick such that it is always generated regardless of the interval.		 jshamlet 2912d 21h /open8_urisc/trunk/VHDL/
175 Added 4 and 8-bit LCD interfaces with backlight and contrast DACs jshamlet 2913d 02h /open8_urisc/trunk/VHDL/
174 Added ROM/RAM wrappers jshamlet 3107d 21h /open8_urisc/trunk/VHDL/
173 Added a couple of useful interfaces for detecting button presses and clock changes. jshamlet 3107d 21h /open8_urisc/trunk/VHDL/
172 General code cleanup jshamlet 3107d 21h /open8_urisc/trunk/VHDL/
171 Fixed comments for offsets 0x0 - 0x3 to indicate the read value jshamlet 3107d 21h /open8_urisc/trunk/VHDL/
170 Added 24-bit resolution epoch timer / alarm clock jshamlet 3107d 21h /open8_urisc/trunk/VHDL/
169 Corrected issue with CMP and SBC generating an inverted carry flag and added new constants to the package file to simplify interfacing new modules. jshamlet 3162d 22h /open8_urisc/trunk/VHDL/
168 Simplified write data path logic,
Converted RTC to packed BCD,
Corrected several bugs in real time clock component,		 jshamlet 3941d 18h /open8_urisc/trunk/VHDL/
167 Updated CPU model; Pipelined ALU control signals to improve fMAX, corrected issue with interrupt controller priority not being obeyed, fixed bug in auto-indexing instructions where the upper register wasn't being properly incremented, cleaned up code to make the processor model easier to follow.
Added several useful modules that use the Open8 bus.		 jshamlet 3949d 16h /open8_urisc/trunk/VHDL/
164 Modified the data path to allow the bus to go idle while waiting for an interrupt. This makes it easier to debug code that uses the WAI instruction, as both Wr_Enable and Rd_Enable go low. jshamlet 4585d 12h /open8_urisc/trunk/VHDL/
162 Added optional generic to specify that the BRK instruction implements a WAit_for_Interrupt (WAI) instruction instead. Logically emulates INT, but without triggering a soft interrupt. Note that the NOP instruction maps to BRK, and will not function correctly if this option is set. jshamlet 4676d 05h /open8_urisc/trunk/VHDL/
156 Optimized for timing,
Flattened block structure to single entity.		 jshamlet 4732d 20h /open8_urisc/trunk/VHDL/
155 Fixed additional interrupt logic bug,
Optimized several blocks - including ALU, stack, program counter, and data path.		 jshamlet 4733d 15h /open8_urisc/trunk/VHDL/
154 Fixed problem with missing data path override in interrupt logic. Should resolve issues with processor crashing when an interrupt occurs as a STO instruction is being executed. jshamlet 4738d 18h /open8_urisc/trunk/VHDL/

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