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[/] [open8_urisc/] [trunk/] [VHDL/] - Rev 214

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Rev Log message Author Age Path
214 Initial add of some older code jshamlet 1539d 13h /open8_urisc/trunk/VHDL/
213 Code and comment cleanup jshamlet 1539d 14h /open8_urisc/trunk/VHDL/
212 Fixed issue with rewritten epoch timer not clearing alarm on set point write. jshamlet 1539d 20h /open8_urisc/trunk/VHDL/
211 Ok, this time with feeling. Timer should now properly reset on interval update. jshamlet 1540d 18h /open8_urisc/trunk/VHDL/
210 Modified the timers to reset on new interval write. This avoids an issue in the original design where the timer had to reach zero before updating, potentially causing unwanted interrupts.
Also added a flag to the CPU to allow interrupts to be processed sequentially based on the state of the I bit. This one is set to false by default, as it is a significant change in interrupt behavior. Long, and reentrant, ISRs can clear the I bit prematurely to allow themselves to be interrupted.
Lastly, added the I bit to the exported flags for possible use in memory protection schemes.		 jshamlet 1540d 20h /open8_urisc/trunk/VHDL/
209 Fixed an issue in the PIT timer that caused an immediate interrupt on interval write,
Fixed an issue in the epoch timer that resulted in a spurious interrupt due to extra LSB's being set by default in the set point register,
While cleaning elsewhere, founding a spacing issue in the CPU HDL,
Added a 4k ROM and MW core.		 jshamlet 1541d 09h /open8_urisc/trunk/VHDL/
208 Removed unnecessary package references jshamlet 1541d 18h /open8_urisc/trunk/VHDL/
207 Added a simple 8-bit, fixed asynchronous serial interface with compile time settable bit-rate, parity enable, and parity mode generics. jshamlet 1542d 11h /open8_urisc/trunk/VHDL/
206 Merged interrupt logic with other clocked process. jshamlet 1546d 06h /open8_urisc/trunk/VHDL/
205 More code and comment cleanup for the new SDLC engine jshamlet 1546d 06h /open8_urisc/trunk/VHDL/
204 Fixed more incorrect comments jshamlet 1546d 07h /open8_urisc/trunk/VHDL/
203 Removed an extra delay FF from the bitclock rising edge signal for the clock slave configuration to better center the rising edge pulse on the receive signal. jshamlet 1546d 13h /open8_urisc/trunk/VHDL/
202 Fixed receiver bug that caused false flag detection,
Split the large sdlc_serial_ctrl entity into sub-entities to make debugging easier.		 jshamlet 1546d 13h /open8_urisc/trunk/VHDL/
201 Fixed comments regarding RX Checksum location jshamlet 1548d 11h /open8_urisc/trunk/VHDL/
200 Renamed dual-port buffer to match other entities. jshamlet 1548d 11h /open8_urisc/trunk/VHDL/
199 Added monitor ram for debugging and fixed issue with dual-port read path. jshamlet 1548d 11h /open8_urisc/trunk/VHDL/
198 Removed debugging memory jshamlet 1548d 19h /open8_urisc/trunk/VHDL/
197 Fixed incorrect comments jshamlet 1548d 19h /open8_urisc/trunk/VHDL/
196 Modified the update logic to allow direct writes to offset 0xFE for refreshing the clock status. This way, any write to the clock status register will immediately be undone. (Writing 0x00 to offset 0xFF is once-more ignored) jshamlet 1548d 20h /open8_urisc/trunk/VHDL/
195 Added dual-port RAM core for SDLC interface. jshamlet 1549d 15h /open8_urisc/trunk/VHDL/

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