| Rev |
Log message |
Author |
Age |
Path |
| 66 |
Fixed the simulator-assisted printf l.nop in cycle accurate, and supporting software. |
julius |
5262d 05h |
/openrisc/trunk/orpsocv2/ |
| 65 |
ORPSoCv2 update: or1200_defines DVRDCR value, verilog testbench uart decoder fix |
julius |
5266d 11h |
/openrisc/trunk/orpsocv2/ |
| 64 |
Trying to fix the system c model jtagsc.h checkout problem, also removed dependency generation in the system c modules makefile. |
julius |
5269d 06h |
/openrisc/trunk/orpsocv2/ |
| 63 |
Finally adding RSP server to cycle accurate model, based on work by Jeremey Bennett but slightly modified for the debug unit we use. Adding binary logging file mode to cycle accurate model which allows smaller and quicker execution logging, along with binary log reader in sw/utils. Adding cycle accurate wishbone bus transaction log generation. still some bugs in CA model for some reason where it skips cycles when logging either execution or bus transactions. Changing or1200 du allowing hardware watchpoints on data load and stores. |
julius |
5279d 03h |
/openrisc/trunk/orpsocv2/ |
| 58 |
ORPSoC2 update - added fpu and implemented in processor, also some sw tests for it, makefile for event sims cleaned up |
julius |
5320d 23h |
/openrisc/trunk/orpsocv2/ |
| 57 |
ORPSoC execution logs created by event sim and cycle accurate should now be equivalent. Changed some of the rule names in orpsoc main makefile to make all rules use hyphens instead of underscores between words |
julius |
5326d 03h |
/openrisc/trunk/orpsocv2/ |
| 56 |
adding generic pll model to orpsoc |
julius |
5334d 05h |
/openrisc/trunk/orpsocv2/ |
| 55 |
Added modelsim support to makefile. Moved buffer libraries to sensible place. Removed a lot of junk |
julius |
5336d 19h |
/openrisc/trunk/orpsocv2/ |
| 54 |
wb_conbus wishbone arbiter now in orpsocv2 instead of synthesized netlist |
julius |
5347d 02h |
/openrisc/trunk/orpsocv2/ |
| 53 |
Fixed incorrect commandline option for ORPSoC and main makefile setting |
julius |
5365d 03h |
/openrisc/trunk/orpsocv2/ |
| 52 |
ORPSoC update - ability to dump part or all of SRAM contents at the end of simulation |
julius |
5365d 23h |
/openrisc/trunk/orpsocv2/ |
| 51 |
ORPSoCv2 updates: cycle accurate profiling, ELF loading |
julius |
5380d 01h |
/openrisc/trunk/orpsocv2/ |
| 50 |
Adding or32_funcs.S |
julius |
5380d 05h |
/openrisc/trunk/orpsocv2/ |
| 49 |
Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update |
julius |
5398d 19h |
/openrisc/trunk/orpsocv2/ |
| 46 |
debug interfaces now support byte and non-aligned accesses from gdb |
julius |
5414d 06h |
/openrisc/trunk/orpsocv2/ |
| 45 |
Orpsoc eth test fix and script error message update |
julius |
5421d 06h |
/openrisc/trunk/orpsocv2/ |
| 44 |
New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades |
julius |
5450d 06h |
/openrisc/trunk/orpsocv2/ |
| 43 |
Couple of fixes to ORPSoC, new linux patch version in toolchain script |
julius |
5474d 03h |
/openrisc/trunk/orpsocv2/ |
| 42 |
Fixed ORPSoCv2 VCD dumping and UART output in cycleaccurate model |
julius |
5489d 23h |
/openrisc/trunk/orpsocv2/ |
| 41 |
Update to or1k top |
julius |
5493d 01h |
/openrisc/trunk/orpsocv2/ |
