OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [nog_patch_38/] - Rev 994

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
994 Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board. lampret 7998d 18h /or1k/tags/nog_patch_38/
993 Fixed IMMU bug. lampret 7998d 18h /or1k/tags/nog_patch_38/
992 A bug when cache enabled and bus error comes fixed. simons 7999d 03h /or1k/tags/nog_patch_38/
991 Different memory controller. simons 7999d 03h /or1k/tags/nog_patch_38/
990 Test is now complete. simons 7999d 03h /or1k/tags/nog_patch_38/
989 c++ is making problems so, for now, it is excluded. simons 8000d 11h /or1k/tags/nog_patch_38/
988 ORP architecture supported. simons 8001d 03h /or1k/tags/nog_patch_38/
987 ORP architecture supported. simons 8001d 10h /or1k/tags/nog_patch_38/
986 outputs out of function are not registered anymore markom 8001d 11h /or1k/tags/nog_patch_38/
985 DTLB translation doesn't work on or1ksim when IC/DC enabled. lampret 8001d 22h /or1k/tags/nog_patch_38/
984 Disable SB until it is tested lampret 8001d 23h /or1k/tags/nog_patch_38/
983 First checkin lampret 8002d 00h /or1k/tags/nog_patch_38/
982 Moved to sim/bin lampret 8002d 00h /or1k/tags/nog_patch_38/
981 First checkin. lampret 8002d 01h /or1k/tags/nog_patch_38/
980 Removed sim.tcl that shouldn't be here. lampret 8002d 01h /or1k/tags/nog_patch_38/
979 Removed old test case binaries. lampret 8002d 01h /or1k/tags/nog_patch_38/
978 Added variable delay for SRAM. lampret 8002d 01h /or1k/tags/nog_patch_38/
977 Added store buffer. lampret 8002d 01h /or1k/tags/nog_patch_38/
976 Added store buffer lampret 8002d 01h /or1k/tags/nog_patch_38/
975 First checkin lampret 8002d 01h /or1k/tags/nog_patch_38/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.