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[/] [or1k/] [tags/] [rel_12/] - Rev 401

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Rev	Log message	Author	Age	Path
401	* empty log message *	simons	8261d 22h	/or1k/tags/rel_12/
400	force_dslot_fetch does not work - allways zero.	simons	8261d 22h	/or1k/tags/rel_12/
399	Trap insn couses break after exits ex_insn.	simons	8261d 22h	/or1k/tags/rel_12/
398	added register field defines	ivang	8264d 04h	/or1k/tags/rel_12/
397	removed or16 architecture	markom	8264d 05h	/or1k/tags/rel_12/
396	added missing file	markom	8264d 07h	/or1k/tags/rel_12/
395	removed obsolete dependency and history from cpu section	markom	8264d 09h	/or1k/tags/rel_12/
394	dependency joined with dependstats; history moved to sim section	markom	8264d 10h	/or1k/tags/rel_12/
393	messages: exception on many places changed to abort	markom	8264d 10h	/or1k/tags/rel_12/
391	Fixed except_stop width and fixed EX PC for 1400444f no-ops.	lampret	8264d 18h	/or1k/tags/rel_12/
390	Changed instantiation name of VS RAMs.	lampret	8264d 20h	/or1k/tags/rel_12/
389	Changed default delay for load and store in superscalar cpu.	lampret	8264d 20h	/or1k/tags/rel_12/
388	Added comments for cpu section.	lampret	8264d 20h	/or1k/tags/rel_12/
387	Now FPGA and ASIC target are separate.	lampret	8264d 22h	/or1k/tags/rel_12/
386	Fixed VS RAM instantiation - again.	lampret	8264d 22h	/or1k/tags/rel_12/
385	check testbench now modified to work with new report output	markom	8265d 04h	/or1k/tags/rel_12/
384	modified simmem.cfg structure! ADD > BEFORE EACH LINE!	markom	8265d 05h	/or1k/tags/rel_12/
383	modified simmem.cfg structure! ADD	markom	8265d 05h	/or1k/tags/rel_12/
382	bitmask function bug fixed	markom	8265d 07h	/or1k/tags/rel_12/
381	number display is more strict with 0x prefix with hex numbers	markom	8265d 07h	/or1k/tags/rel_12/

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[/] [or1k/] [tags/] [rel_12/] - Rev 401

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