OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [stable_0_2_0_rc2/] - Rev 924

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
924 bb joining, basic block triggers bugs fixed; more verilog generation of arbiter markom 8018d 00h /or1k/tags/stable_0_2_0_rc2/
923 basic dos/fat service release rherveille 8018d 15h /or1k/tags/stable_0_2_0_rc2/
922 basic dos service rherveille 8018d 15h /or1k/tags/stable_0_2_0_rc2/
921 atabug stable release rherveille 8018d 15h /or1k/tags/stable_0_2_0_rc2/
920 *** empty log message *** rherveille 8018d 15h /or1k/tags/stable_0_2_0_rc2/
919 stable release rherveille 8018d 16h /or1k/tags/stable_0_2_0_rc2/
918 sa command bug fixed markom 8018d 22h /or1k/tags/stable_0_2_0_rc2/
917 optimize cmovs bug fixed markom 8018d 22h /or1k/tags/stable_0_2_0_rc2/
916 MAC now follows software convention (signed multiply instead of unsigned). lampret 8019d 08h /or1k/tags/stable_0_2_0_rc2/
915 cuc main verilog file generation markom 8019d 19h /or1k/tags/stable_0_2_0_rc2/
914 SR[FO] is always set to 1. lampret 8020d 00h /or1k/tags/stable_0_2_0_rc2/
913 Executed log insns counter output in decimal instead of hex. lampret 8020d 01h /or1k/tags/stable_0_2_0_rc2/
912 Reset SR (and ESR) have TEE set to zero (no tick timer). lampret 8020d 01h /or1k/tags/stable_0_2_0_rc2/
911 Added instruction count to hardware executed log lampret 8020d 01h /or1k/tags/stable_0_2_0_rc2/
910 No arith and overflow flags by default. lampret 8020d 01h /or1k/tags/stable_0_2_0_rc2/
909 Bug fix. lampret 8021d 12h /or1k/tags/stable_0_2_0_rc2/
908 busy signal added markom 8025d 20h /or1k/tags/stable_0_2_0_rc2/
907 function calling generation; not tested yet markom 8025d 20h /or1k/tags/stable_0_2_0_rc2/
906 function dependency analysis added markom 8025d 23h /or1k/tags/stable_0_2_0_rc2/
905 type 2 bb joining; few small bugs fixed; cmov edge condition added markom 8026d 19h /or1k/tags/stable_0_2_0_rc2/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.