URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [trunk/] - Rev 1000

Rev	Log message	Author	Age	Path
1000	IC/DC cache enable routines fixed.	simons	8029d 00h	/or1k/trunk/
999	Now every ramdisk image should have init program.	simons	8029d 01h	/or1k/trunk/
998	added missing fout initialization	markom	8029d 03h	/or1k/trunk/
997	PRINTF should be used instead of printf; command redirection repaired	markom	8029d 04h	/or1k/trunk/
996	some minor bugs fixed	markom	8030d 02h	/or1k/trunk/
994	Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board.	lampret	8030d 10h	/or1k/trunk/
993	Fixed IMMU bug.	lampret	8030d 10h	/or1k/trunk/
992	A bug when cache enabled and bus error comes fixed.	simons	8030d 19h	/or1k/trunk/
991	Different memory controller.	simons	8030d 19h	/or1k/trunk/
990	Test is now complete.	simons	8030d 19h	/or1k/trunk/
989	c++ is making problems so, for now, it is excluded.	simons	8032d 03h	/or1k/trunk/
988	ORP architecture supported.	simons	8032d 19h	/or1k/trunk/
987	ORP architecture supported.	simons	8033d 02h	/or1k/trunk/
986	outputs out of function are not registered anymore	markom	8033d 03h	/or1k/trunk/
985	DTLB translation doesn't work on or1ksim when IC/DC enabled.	lampret	8033d 14h	/or1k/trunk/
984	Disable SB until it is tested	lampret	8033d 14h	/or1k/trunk/
983	First checkin	lampret	8033d 16h	/or1k/trunk/
982	Moved to sim/bin	lampret	8033d 16h	/or1k/trunk/
981	First checkin.	lampret	8033d 16h	/or1k/trunk/
980	Removed sim.tcl that shouldn't be here.	lampret	8033d 16h	/or1k/trunk/