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[/] [pci/] [tags/] [asyst_3/] - Rev 76

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Rev Log message Author Age Path
76 TRDY output delay was 10 instead of 11. Repaired. mihad 7839d 16h /pci/tags/asyst_3/
75 Include statement moved out of off/on pragma as reported by Uwe. mihad 7842d 16h /pci/tags/asyst_3/
73 Bug fixes, testcases added. mihad 7842d 17h /pci/tags/asyst_3/
72 *** empty log message *** mihad 7889d 20h /pci/tags/asyst_3/
71 Changed the code a bit to make it more readable.
Functionality not changed in any way.
More robust synchronization in fifos is still pending.		 mihad 7897d 12h /pci/tags/asyst_3/
69 Changed BIST signal names etc.. mihad 7934d 20h /pci/tags/asyst_3/
68 Changed wrong signal name scanb_sen into scanb_en. tadejm 7938d 05h /pci/tags/asyst_3/
67 Changed BIST signals for RAMs. tadejm 7938d 10h /pci/tags/asyst_3/
66 Changed empty status generation in pciw_fifo_control.v mihad 7941d 20h /pci/tags/asyst_3/
65 Cleaned up non-blocking assignments in combinatinal logic statements mihad 7944d 19h /pci/tags/asyst_3/
64 The testcase I just added in previous revision repaired mihad 7944d 21h /pci/tags/asyst_3/
63 Added additional testcase and changed rst name in BIST to trst mihad 7944d 23h /pci/tags/asyst_3/
62 Added BIST signals for RAMs. mihad 7947d 16h /pci/tags/asyst_3/
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 7955d 15h /pci/tags/asyst_3/
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 7955d 17h /pci/tags/asyst_3/
58 Removed all logic from asynchronous reset network mihad 7960d 17h /pci/tags/asyst_3/
57 Added completion expiration test for WB Slave unit. Changed expiration signalling mihad 7960d 23h /pci/tags/asyst_3/
56 Number of state bits define was removed mihad 7961d 14h /pci/tags/asyst_3/
55 Changed state machine encoding to true one-hot mihad 7961d 14h /pci/tags/asyst_3/
54 Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim mihad 7994d 16h /pci/tags/asyst_3/

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