URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_12/] [rtl/] - Rev 110

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
110	Module that converts slave WISHBONE B3 accesses to WISHBONE B2 accesses with CAB.	mihad	7707d 18h	/pci/tags/rel_12/rtl/
108	Added 'three_left_out' to pci_pciw_fifo signaling three locations before full. Added comparison between current registered cbe and next unregistered cbe to signal wb_master whether it is allowed to performe burst or not. Due to this, I needed 'three_left_out' so that writing to pci_pciw_fifo can be registered, otherwise timing problems would occure.	tadejm	7711d 15h	/pci/tags/rel_12/rtl/
106	Added limited WISHBONE B3 support for WISHBONE Slave Unit. Doesn't support full speed bursts yet.	mihad	7716d 14h	/pci/tags/rel_12/rtl/
104	Found and simulated the problem in the synchronization logic. Repaired the synchronization logic in the FIFOs.	mihad	7721d 23h	/pci/tags/rel_12/rtl/
94	Changed one critical PCI bus signal logic.	mihad	7768d 22h	/pci/tags/rel_12/rtl/
88	Added the reset value parameter to the synchronizer flop module. Added resets to all synchronizer flop instances. Repaired initial sync value in fifos.	mihad	7846d 18h	/pci/tags/rel_12/rtl/
86	Entered the option to disable no response counter in wb master.	mihad	7858d 16h	/pci/tags/rel_12/rtl/
83	Cleaned up the code. No functional changes.	mihad	7887d 13h	/pci/tags/rel_12/rtl/
81	Updated synchronization in top level fifo modules.	mihad	7901d 10h	/pci/tags/rel_12/rtl/
79	Updated.	mihad	7904d 15h	/pci/tags/rel_12/rtl/
78	Old files with wrong names removed.	mihad	7904d 15h	/pci/tags/rel_12/rtl/
77	Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.	mihad	7904d 15h	/pci/tags/rel_12/rtl/
73	Bug fixes, testcases added.	mihad	7910d 16h	/pci/tags/rel_12/rtl/
72	* empty log message *	mihad	7957d 19h	/pci/tags/rel_12/rtl/
71	Changed the code a bit to make it more readable. Functionality not changed in any way. More robust synchronization in fifos is still pending.	mihad	7965d 11h	/pci/tags/rel_12/rtl/
69	Changed BIST signal names etc..	mihad	8002d 19h	/pci/tags/rel_12/rtl/
68	Changed wrong signal name scanb_sen into scanb_en.	tadejm	8006d 04h	/pci/tags/rel_12/rtl/
67	Changed BIST signals for RAMs.	tadejm	8006d 09h	/pci/tags/rel_12/rtl/
66	Changed empty status generation in pciw_fifo_control.v	mihad	8009d 19h	/pci/tags/rel_12/rtl/
65	Cleaned up non-blocking assignments in combinatinal logic statements	mihad	8012d 18h	/pci/tags/rel_12/rtl/

1 2 Next >

Show All

Browse

Tools

Subversion Repositories pci

[/] [pci/] [tags/] [rel_12/] [rtl/] - Rev 110

Filtering Options