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[/] [pci/] [tags/] [rel_7/] - Rev 90

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Rev	Log message	Author	Age	Path
90	WebPack 5.2 project file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de)	tadejm	7795d 02h	/pci/tags/rel_7/
89	Burst 2 error fixed.	mihad	7831d 03h	/pci/tags/rel_7/
88	Added the reset value parameter to the synchronizer flop module. Added resets to all synchronizer flop instances. Repaired initial sync value in fifos.	mihad	7837d 02h	/pci/tags/rel_7/
87	Updated acording to RTL changes.	mihad	7848d 23h	/pci/tags/rel_7/
86	Entered the option to disable no response counter in wb master.	mihad	7848d 23h	/pci/tags/rel_7/
85	Changed Vendor ID defines.	mihad	7849d 04h	/pci/tags/rel_7/
84	Changed vendor ID.	mihad	7852d 22h	/pci/tags/rel_7/
83	Cleaned up the code. No functional changes.	mihad	7877d 20h	/pci/tags/rel_7/
81	Updated synchronization in top level fifo modules.	mihad	7891d 17h	/pci/tags/rel_7/
79	Updated.	mihad	7894d 22h	/pci/tags/rel_7/
78	Old files with wrong names removed.	mihad	7894d 22h	/pci/tags/rel_7/
77	Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.	mihad	7894d 22h	/pci/tags/rel_7/
76	TRDY output delay was 10 instead of 11. Repaired.	mihad	7897d 22h	/pci/tags/rel_7/
75	Include statement moved out of off/on pragma as reported by Uwe.	mihad	7900d 22h	/pci/tags/rel_7/
73	Bug fixes, testcases added.	mihad	7900d 23h	/pci/tags/rel_7/
72	* empty log message *	mihad	7948d 02h	/pci/tags/rel_7/
71	Changed the code a bit to make it more readable. Functionality not changed in any way. More robust synchronization in fifos is still pending.	mihad	7955d 18h	/pci/tags/rel_7/
69	Changed BIST signal names etc..	mihad	7993d 02h	/pci/tags/rel_7/
68	Changed wrong signal name scanb_sen into scanb_en.	tadejm	7996d 11h	/pci/tags/rel_7/
67	Changed BIST signals for RAMs.	tadejm	7996d 16h	/pci/tags/rel_7/

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Subversion Repositories pci

[/] [pci/] [tags/] [rel_7/] - Rev 90

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