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[/] [pci/] [tags/] [rel_7/] [rtl/] [verilog/] - Rev 88

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Rev	Log message	Author	Age	Path
88	Added the reset value parameter to the synchronizer flop module. Added resets to all synchronizer flop instances. Repaired initial sync value in fifos.	mihad	7766d 16h	/pci/tags/rel_7/rtl/verilog/
86	Entered the option to disable no response counter in wb master.	mihad	7778d 14h	/pci/tags/rel_7/rtl/verilog/
83	Cleaned up the code. No functional changes.	mihad	7807d 11h	/pci/tags/rel_7/rtl/verilog/
81	Updated synchronization in top level fifo modules.	mihad	7821d 07h	/pci/tags/rel_7/rtl/verilog/
79	Updated.	mihad	7824d 12h	/pci/tags/rel_7/rtl/verilog/
78	Old files with wrong names removed.	mihad	7824d 12h	/pci/tags/rel_7/rtl/verilog/
77	Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.	mihad	7824d 13h	/pci/tags/rel_7/rtl/verilog/
73	Bug fixes, testcases added.	mihad	7830d 13h	/pci/tags/rel_7/rtl/verilog/
72	* empty log message *	mihad	7877d 17h	/pci/tags/rel_7/rtl/verilog/
71	Changed the code a bit to make it more readable. Functionality not changed in any way. More robust synchronization in fifos is still pending.	mihad	7885d 09h	/pci/tags/rel_7/rtl/verilog/
69	Changed BIST signal names etc..	mihad	7922d 16h	/pci/tags/rel_7/rtl/verilog/
68	Changed wrong signal name scanb_sen into scanb_en.	tadejm	7926d 02h	/pci/tags/rel_7/rtl/verilog/
67	Changed BIST signals for RAMs.	tadejm	7926d 06h	/pci/tags/rel_7/rtl/verilog/
66	Changed empty status generation in pciw_fifo_control.v	mihad	7929d 17h	/pci/tags/rel_7/rtl/verilog/
65	Cleaned up non-blocking assignments in combinatinal logic statements	mihad	7932d 15h	/pci/tags/rel_7/rtl/verilog/
63	Added additional testcase and changed rst name in BIST to trst	mihad	7932d 19h	/pci/tags/rel_7/rtl/verilog/
62	Added BIST signals for RAMs.	mihad	7935d 12h	/pci/tags/rel_7/rtl/verilog/
60	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!	mihad	7943d 12h	/pci/tags/rel_7/rtl/verilog/
59	Added meta flop module for easier meta stable FF identification during synthesis	mihad	7943d 13h	/pci/tags/rel_7/rtl/verilog/
58	Removed all logic from asynchronous reset network	mihad	7948d 13h	/pci/tags/rel_7/rtl/verilog/

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[/] [pci/] [tags/] [rel_7/] [rtl/] [verilog/] - Rev 88

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