OpenCores
URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_8/] [rtl/] - Rev 77

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7870d 01h /pci/tags/rel_8/rtl/
73 Bug fixes, testcases added. mihad 7876d 01h /pci/tags/rel_8/rtl/
72 *** empty log message *** mihad 7923d 05h /pci/tags/rel_8/rtl/
71 Changed the code a bit to make it more readable.
Functionality not changed in any way.
More robust synchronization in fifos is still pending.
mihad 7930d 21h /pci/tags/rel_8/rtl/
69 Changed BIST signal names etc.. mihad 7968d 04h /pci/tags/rel_8/rtl/
68 Changed wrong signal name scanb_sen into scanb_en. tadejm 7971d 14h /pci/tags/rel_8/rtl/
67 Changed BIST signals for RAMs. tadejm 7971d 18h /pci/tags/rel_8/rtl/
66 Changed empty status generation in pciw_fifo_control.v mihad 7975d 05h /pci/tags/rel_8/rtl/
65 Cleaned up non-blocking assignments in combinatinal logic statements mihad 7978d 03h /pci/tags/rel_8/rtl/
63 Added additional testcase and changed rst name in BIST to trst mihad 7978d 07h /pci/tags/rel_8/rtl/
62 Added BIST signals for RAMs. mihad 7981d 00h /pci/tags/rel_8/rtl/
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 7989d 00h /pci/tags/rel_8/rtl/
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 7989d 01h /pci/tags/rel_8/rtl/
58 Removed all logic from asynchronous reset network mihad 7994d 01h /pci/tags/rel_8/rtl/
57 Added completion expiration test for WB Slave unit. Changed expiration signalling mihad 7994d 07h /pci/tags/rel_8/rtl/
56 Number of state bits define was removed mihad 7994d 22h /pci/tags/rel_8/rtl/
55 Changed state machine encoding to true one-hot mihad 7994d 23h /pci/tags/rel_8/rtl/
53 Updated for synthesis purposes. Gate level simulation was failing in some configurations mihad 8028d 04h /pci/tags/rel_8/rtl/
51 Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions. mihad 8028d 08h /pci/tags/rel_8/rtl/
50 Got rid of undef directives mihad 8031d 00h /pci/tags/rel_8/rtl/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.