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Rev Log message Author Age Path
38 Add "Hello World" test application skordal 3310d 18h /potato/
37 Add macro to set the TOHOST register from C code skordal 3310d 18h /potato/
36 Ensure correct read of CSR after stall skordal 3310d 18h /potato/
35 Prevent jumping/branching when stalling skordal 3310d 18h /potato/
34 Prevent flushing the pipeline if it is stalling skordal 3310d 18h /potato/
33 Ensure correct read of CSR after stall skordal 3310d 18h /potato/
32 Prevent jumping/branching when stalling skordal 3313d 16h /potato/
31 Prevent flushing the pipeline if it is stalling skordal 3313d 17h /potato/
30 Add testcase for a combination of instructions that fail when using cache skordal 3315d 21h /potato/
29 Add reset functionality for the WB arbiter state machine skordal 3318d 16h /potato/
28 Add rudimentary User's manual skordal 3324d 16h /potato/
27 Prevent exceptions from being taken while stalling skordal 3324d 18h /potato/
26 Prevent exceptions from being taken while stalling

Jumping to an exception handler while stalling and waiting for a load/store
instruction to finish can cause undefined results from the load/store
instruction. This actually fixes the issue mentioned in revision r20.		 skordal 3324d 20h /potato/
25 Add placeholder cache modules and a wishbone arbiter skordal 3327d 01h /potato/
24 Remove unused STRINGIFY macros skordal 3327d 14h /potato/
23 Create branch to use for implementing a cache skordal 3327d 14h /potato/
22 Fix the potato_get_badvaddr() macro skordal 3327d 15h /potato/
21 Upgrade the example design to use a 60 MHz system clock skordal 3327d 15h /potato/
20 Fix SHA256 benchmark crash by storing all registers on exception handler entry

This problem will disappear when the processor is updated to conform to the
new supervisor specification, which will allow us to use a compiler that
conforms to the new "official" ABI.		 skordal 3327d 15h /potato/
19 SHA256 benchmark: allow compiler to inline at will skordal 3327d 15h /potato/

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