URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] - Rev 59

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
59	Control path request and data are register now for better FPGA timing	dinesha	4506d 09h	/sdr_ctrl/trunk/
58	Read Data is register on RD_FAST=0 case	dinesha	4506d 09h	/sdr_ctrl/trunk/
57	Synthesis constraints are added	dinesha	4507d 00h	/sdr_ctrl/trunk/
56	FPGA Synth optimisation	dinesha	4507d 01h	/sdr_ctrl/trunk/
55	FPGA Synthesis timing optimisation	dinesha	4507d 01h	/sdr_ctrl/trunk/
54	FPGA Timing Optimisation	dinesha	4509d 23h	/sdr_ctrl/trunk/
53	Test bench upgradation	dinesha	4510d 23h	/sdr_ctrl/trunk/
52	Documentation update for request control and transfer control block	dinesha	4510d 23h	/sdr_ctrl/trunk/
51	FPGA relating timing optimisation done	dinesha	4511d 00h	/sdr_ctrl/trunk/
50	Bug fix the request length is fixe	dinesha	4513d 03h	/sdr_ctrl/trunk/
49	clean up	dinesha	4514d 02h	/sdr_ctrl/trunk/
48	top-level cleanup	dinesha	4514d 03h	/sdr_ctrl/trunk/
47	SDRAM bus converter bug fix and top-level signal clean up	dinesha	4514d 03h	/sdr_ctrl/trunk/
46	test bench upgrade + rtl cleanup	dinesha	4516d 03h	/sdr_ctrl/trunk/
45	RTL clean up and logic seperation done from sdram bus converter and request generator	dinesha	4516d 08h	/sdr_ctrl/trunk/
44	SDRAM data path logic is modified to support 4 command line pipe line of different bank	dinesha	4518d 06h	/sdr_ctrl/trunk/
43	Test bench automation to handle differ write/read burst sequence is supported now	dinesha	4518d 07h	/sdr_ctrl/trunk/
42	Bug fix in read access is fixed	dinesha	4518d 07h	/sdr_ctrl/trunk/
41	Updated Spec ver 0.1 is added back to svn	dinesha	4518d 09h	/sdr_ctrl/trunk/
40	Application layer Fifo full conditional are register now to synth timing fixes	dinesha	4519d 02h	/sdr_ctrl/trunk/

1 2 Next >

Show All

Browse

Tools

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] - Rev 59

Filtering Options